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Searched refs:subregs (Results 1 – 25 of 58) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCRegisterInfoDMR.td44 class DMRROWp<bits<5> num, string n, list<Register> subregs> : PPCReg<n> {
46 let SubRegs = subregs;
49 // WACC - Wide ACC registers. Accumulator registers that are subregs of DMR.
50 // These ACC registers no longer include VSR regs as subregs.
51 class WACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
53 let SubRegs = subregs;
59 class WACC_HI<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
61 let SubRegs = subregs;
64 class DMR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
66 let SubRegs = subregs;
[all …]
DPPCRegisterInfoMMA.td20 class ACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
22 let SubRegs = subregs;
29 class UACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
31 let SubRegs = subregs;
DPPCRegisterInfo.td91 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
93 let SubRegs = subregs;
102 class VSRPair<bits<5> num, string n, list<Register> subregs> : PPCReg<n> {
104 let SubRegs = subregs;
/openbsd/src/gnu/llvm/llvm/lib/Target/VE/
DVERegisterInfo.td13 class VEReg<bits<7> enc, string n, list<Register> subregs = [],
19 let SubRegs = subregs;
29 class VEVecReg<bits<8> enc, string n, list<Register> subregs = [],
35 let SubRegs = subregs;
39 class VEMaskReg<bits<4> enc, string n, list<Register> subregs = [],
45 let SubRegs = subregs;
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsRegisterInfo.td34 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
35 : RegisterWithSubRegs<n, subregs> {
44 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
45 : MipsRegWithSubRegs<Enc, n, subregs> {
53 class AFPR<bits<16> Enc, string n, list<Register> subregs>
54 : MipsRegWithSubRegs<Enc, n, subregs> {
59 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
60 : MipsRegWithSubRegs<Enc, n, subregs> {
66 class AFPR128<bits<16> Enc, string n, list<Register> subregs>
67 : MipsRegWithSubRegs<Enc, n, subregs> {
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/BPF/
DBPFRegisterInfo.td24 class Ri<bits<16> Enc, string n, list<Register> subregs>
25 : RegisterWithSubRegs<n, subregs> {
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td27 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs,
29 RegisterWithSubRegs<n, subregs> {
40 class HexagonDoubleSys<bits<7> num, string n, list<Register> subregs,
42 RegisterWithSubRegs<n, subregs> {
63 class Rd<bits<5> num, string n, list<Register> subregs,
65 HexagonDoubleReg<num, n, subregs, alt> {
66 let SubRegs = subregs;
84 class Rcc<bits<5> num, string n, list<Register> subregs,
86 HexagonDoubleReg<num, n, subregs, alt> {
87 let SubRegs = subregs;
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td12 class LanaiReg<bits<5> num, string n, list<Register> subregs = [],
17 let SubRegs = subregs;
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DR600RegisterInfo.td19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
20 RegisterWithSubRegs<n, subregs> {
28 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
29 RegisterWithSubRegs<n, subregs> {
/openbsd/src/gnu/llvm/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.td21 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs,
23 : RegisterWithSubRegs<n, subregs> {
/openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td35 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
36 let SubRegs = subregs;
44 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
45 let SubRegs = subregs;
51 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
52 let SubRegs = subregs;
/openbsd/src/gnu/llvm/lldb/source/Plugins/ABI/X86/
DABIX86.cpp59 llvm::ArrayRef<RegData *> subregs, uint32_t base_size, in addPartialRegisters() argument
62 for (const RegData *subreg : subregs) { in addPartialRegisters()
/openbsd/src/gnu/gcc/gcc/config/m32c/
Dpredicates.md48 ; subregs for type changing, but not for size changing.
139 ; Likewise, plus TRUE for subregs.
161 ; Likewise, plus true for subregs.
/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/
DAVRRegisterInfo.td14 class AVRReg<bits<16> num, string name, list<Register> subregs = [],
15 list<string> altNames = []> : RegisterWithSubRegs<name, subregs> {
20 let SubRegs = subregs;
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td17 class SystemZRegWithSubregs<string n, list<Register> subregs>
18 : RegisterWithSubRegs<n, subregs> {
142 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMRegisterInfo.td16 class ARMReg<bits<16> Enc, string n, list<Register> subregs = [],
20 let SubRegs = subregs;
466 // 32-bit SPR subregs).
490 // Subset of QPR that have 32-bit SPR subregs.
496 // Subset of QPR that have DPR_8 and SPR_8 subregs.
/openbsd/src/gnu/gcc/gcc/config/sh/
Dpredicates.md134 ;; subregs, because this would lead to missing sign extensions when
373 ;; are subregs of system registers.
522 ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DMachinePassRegistry.def185 DUMMY_MACHINE_FUNCTION_PASS("rename-independent-subregs", RenameIndependentSubregsPass, ())
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86RegisterInfo.td15 class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
18 let SubRegs = subregs;
592 // Represents the lower 16 registers that have VEX/legacy encodable subregs.
/openbsd/src/gnu/gcc/gcc/config/m32r/
Dm32r.c1651 int subregs = 0; in m32r_legitimize_pic_address() local
1658 subregs = 1; in m32r_legitimize_pic_address()
1661 if (subregs) in m32r_legitimize_pic_address()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td45 class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
47 : RegisterWithSubRegs<n, subregs> {
/openbsd/src/gnu/llvm/llvm/include/llvm/MC/
DMCRegisterInfo.h309 iterator_range<mc_subreg_iterator> subregs(MCRegister Reg) const { in subregs() function
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DRegisterScavenging.cpp202 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) in forward()
DMachineVerifier.cpp133 append_range(RV, TRI->subregs(Reg.asMCReg())); in addRegWithSubRegs()
2474 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) { in checkLiveness()
2493 if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg)) in checkLiveness()
/openbsd/src/gnu/llvm/llvm/
DCREDITS.TXT276 D: vreg subreg infrastructure, X86 codegen improvements based on subregs

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