| /openbsd/src/gnu/usr.bin/perl/t/op/ |
| D | bop.t | 151 sub stores { tied($_[0])->{value} = tied($_[0])->{orig};
163 is(stores($x), 0);
164 is(stores($y), 0);
169 is(stores($x), 0);
170 is(stores($y), 0);
175 is(stores($x), 0);
176 is(stores($y), 0);
181 is(stores($x), 1);
182 is(stores($y), 0);
187 is(stores($x), 1);
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| D | range.t | 383 sub stores { tied($_[0])->{value} = tied($_[0])->{orig};
394 is(stores($x), 0);
400 is(stores($x), 0);
406 is(stores($x), 0);
415 is(stores($x), 0);
424 is(stores($x), 0);
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| /openbsd/src/gnu/gcc/gcc/ |
| D | tree-ssa-dse.c | 75 bitmap stores; member
83 bitmap stores; member
150 if (bd->stores) in dse_initialize_block_local_data()
151 bitmap_clear (bd->stores); in dse_initialize_block_local_data()
297 record_voperand_set (dse_gd->stores, &bd->stores, ann->uid); in dse_optimize_stmt()
309 && bitmap_bit_p (dse_gd->stores, get_stmt_uid (use_stmt))) in dse_optimize_stmt()
330 && bitmap_bit_p (dse_gd->stores, get_stmt_uid (use_stmt)) in dse_optimize_stmt()
359 record_voperand_set (dse_gd->stores, &bd->stores, ann->uid); in dse_optimize_stmt()
375 record_voperand_set (dse_gd->stores, in dse_record_phis()
376 &bd->stores, in dse_record_phis()
[all …]
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| D | flow.c | 213 rtx stores; member
2088 rcli->stores = const0_rtx; in init_propagate_block_info()
3119 rcli->stores = cond; in mark_regno_cond_dead()
3136 if (rcli->stores == const0_rtx) in mark_regno_cond_dead()
3137 rcli->stores = cond; in mark_regno_cond_dead()
3138 else if (rcli->stores != const1_rtx) in mark_regno_cond_dead()
3139 rcli->stores = ior_reg_cond (rcli->stores, cond, 1); in mark_regno_cond_dead()
3150 || (ncond == rcli->orig_condition && rcli->stores == const1_rtx)) in mark_regno_cond_dead()
3193 if (rcli->stores != const0_rtx && rcli->stores != const1_rtx) in flush_reg_cond_reg_1()
3194 rcli->stores = elim_reg_cond (rcli->stores, regno); in flush_reg_cond_reg_1()
[all …]
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| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | Atomics.rst | 36 pair of volatile stores. On the other hand, a non-volatile non-atomic load can
54 because any optimization dealing with stores needs to be aware of it.
101 For cases where simple loads and stores are not sufficient, LLVM provides
106 non-atomic loads and stores, but provide additional guarantees in situations
152 The rule is essentially that all memory accessed with basic loads and stores
156 variable. Note that NotAtomic volatile loads and stores are not properly
163 otherwise exist is allowed; introducing stores to shared variables is not. See
169 unaligned stores: it is not allowed in general to convert an unaligned store
170 into two aligned stores of the same width as the unaligned store. Backends are
196 stores.)
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| D | AssignmentTracking.md | 48 mapping of stores<->markers that can be used to find markers that need to be
49 updated when stores are modified.
151 **Merging** stores: In many cases no change is required as `DIAssignID`
154 becomes linked to all the `llvm.dbg.assign` intrinsics that the merged stores
158 **Inlining** stores: As stores are inlined we generate `llvm.dbg.assign`
159 intrinsics and `DIAssignID` attachments as if the stores represent source
160 assignments, just like the in frontend. This isn’t perfect, as stores may have
164 **Splitting** stores: SROA and passes that split stores treat `llvm.dbg.assign`
167 the `ValueExpression`, and give the split stores (and cloned intrinsics) new
168 `DIAssignID` attachments each. In other words, treat the split stores as
[all …]
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| D | BigEndianNEON.rst | 11 …dian ARM processors is for the most part straightforward. NEON loads and stores however have some …
13 The aim of this document is to explain the problem with NEON loads and stores, and the solution tha…
152 … was chosen as the canonical vector load instruction (and by inference, ``ST1`` for vector stores).
159 … that they are never allowed to be selected to generate vector loads and stores. The exception is …
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| /openbsd/src/gnu/usr.bin/binutils/gas/doc/ |
| D | c-v850.texi | 263 Computes the higher 16 bits of the given expression and stores it into
275 Computes the lower 16 bits of the given expression and stores it into
288 and stores the result into the immediate operand field of the given
303 stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction
304 stores 0xFFFFFFFF into r6 - the right value.
308 Computes the 32 bit value of the given expression and stores it into
321 stores the result as a 16 bit signed value in the immediate operand
338 stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
353 Computes the offset of the named variable from address 0 and stores the
368 register) and stores the result a 6 or 16 bit unsigned value in the
|
| /openbsd/src/gnu/usr.bin/binutils-2.17/gas/doc/ |
| D | c-v850.texi | 263 Computes the higher 16 bits of the given expression and stores it into
275 Computes the lower 16 bits of the given expression and stores it into
288 and stores the result into the immediate operand field of the given
303 stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction
304 stores 0xFFFFFFFF into r6 - the right value.
308 Computes the 32 bit value of the given expression and stores it into
321 stores the result as a 16 bit signed value in the immediate operand
338 stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
353 Computes the offset of the named variable from address 0 and stores the
368 register) and stores the result a 6 or 16 bit unsigned value in the
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.cpp | 417 if (Summary.stores == 1 && SafeToMoveToSlot0) in restrictStoreLoadOrder()
420 else if (Summary.stores >= 1) { in restrictStoreLoadOrder()
432 if (Summary.store1 && Summary.stores > 1) { in restrictStoreLoadOrder()
516 ++Summary.stores; in GetPacketSummary()
524 ++Summary.stores; in GetPacketSummary()
544 ++Summary.stores; in GetPacketSummary()
|
| /openbsd/src/gnu/gcc/gcc/doc/ |
| D | headerdirs.texi | 9 where GCC stores its private include files, and also where GCC
10 stores the fixed include files. A cross compiled GCC runs
|
| /openbsd/src/gnu/usr.bin/gcc/gcc/doc/ |
| D | headerdirs.texi | 9 where GCC stores its private include files, and also where GCC
10 stores the fixed include files. A cross compiled GCC runs
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.td | 17 // Force dependencies for vector trunc stores
|
| /openbsd/src/gnu/usr.bin/binutils-2.17/bfd/doc/ |
| D | reloc.texi | 1654 This is a 48 bit reloc for the FR30 that stores 32 bits.
1657 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1661 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1665 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1669 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1673 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1677 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1681 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1742 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1746 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
[all …]
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| /openbsd/src/gnu/usr.bin/binutils/bfd/doc/ |
| D | reloc.texi | 1401 This is a 48 bit reloc for the FR30 that stores 32 bits.
1404 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1408 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1412 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1416 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1420 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1424 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1428 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1489 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1493 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
[all …]
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| /openbsd/src/gnu/llvm/compiler-rt/lib/msan/ |
| D | msan_flags.inc | 34 "Like malloc_context_size, but for uninit stores.")
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64InstrAtomics.td | 156 // Atomic stores
177 // 8-bit stores
195 // 16-bit stores
213 // 32-bit stores
231 // 64-bit stores
249 // FP 32-bit stores
265 // FP 64-bit stores
|
| /openbsd/src/gnu/usr.bin/gcc/gcc/ |
| D | flow.c | 224 rtx stores; member
1975 rcli->stores = const0_rtx;
2948 rcli->stores = cond;
2965 if (rcli->stores == const0_rtx)
2966 rcli->stores = cond;
2967 else if (rcli->stores != const1_rtx)
2968 rcli->stores = ior_reg_cond (rcli->stores, cond, 1);
2979 || (ncond == rcli->orig_condition && rcli->stores == const1_rtx))
3025 if (rcli->stores != const0_rtx && rcli->stores != const1_rtx)
3026 rcli->stores = elim_reg_cond (rcli->stores, regno);
[all …]
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Target/GlobalISel/ |
| D | SelectionDAGCompat.td | 28 // stores this information in the MachineMemoryOperand.
183 // G_STORE handles both atomic and non-atomic stores where as SelectionDAG had
184 // separate nodes for them. This GINodeEquiv maps the non-atomic stores to
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrAtomics.td | 184 // Atomic stores
211 // Truncating stores.
218 // Fragments for truncating stores.
221 // instructions, we just need to match bare atomic stores. On the other hand,
222 // truncating stores from i64 values are once truncated to i32 first.
230 // Truncating stores with no constant offset
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 1046 void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores, in reduceHugeMemNodeMaps() argument
1048 LLVM_DEBUG(dbgs() << "Before reduction:\nStoring SUnits:\n"; stores.dump(); in reduceHugeMemNodeMaps()
1053 NodeNums.reserve(stores.size() + loads.size()); in reduceHugeMemNodeMaps()
1054 for (const auto &[V, SUs] : stores) { in reduceHugeMemNodeMaps()
1089 insertBarrierChain(stores); in reduceHugeMemNodeMaps()
1092 LLVM_DEBUG(dbgs() << "After reduction:\nStoring SUnits:\n"; stores.dump(); in reduceHugeMemNodeMaps()
|
| /openbsd/src/gnu/gcc/gcc/config/mt/ |
| D | mt.opt | 24 Use byte loads and stores when generating code.
|
| /openbsd/src/gnu/llvm/llvm/docs/Frontend/ |
| D | PerformanceTips.rst | 67 Avoid loads and stores of large aggregate type
70 LLVM currently does not optimize well loads and stores of large :ref:`aggregate
103 ARM ISAs) then the hardware does not handle unaligned loads and stores, and
120 Note that if your loads and stores are atomic, the backend will be unable to
122 As a result, alignment is mandatory for atomic loads and stores.
|
| /openbsd/src/gnu/llvm/llvm/docs/HistoricalNotes/ |
| D | 2001-02-13-Reference-Memory.txt | 28 A. If you do pointer analysis and realize that two stores are
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMScheduleM55.td | 275 // Same as M55Write2IntE3/M55Write2FloatE3 above, but longer latency and no forwarding into stores
327 // Normal stores
329 // Pre/post inc stores
331 // Scatter stores
334 // Interleaving stores
|