| /openbsd/src/sys/dev/pci/drm/radeon/ |
| D | radeon_clocks.c | 46 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
52 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
117 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
156 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
157 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
200 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
234 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
235 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
270 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
298 if (spll->reference_div < 2) in radeon_get_clock_info()
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| D | radeon_combios.c | 729 struct radeon_pll *spll = &rdev->clock.spll; in radeon_combios_get_clock_info() local
756 spll->reference_freq = RBIOS16(pll_info + 0x1a); in radeon_combios_get_clock_info()
757 spll->reference_div = RBIOS16(pll_info + 0x1c); in radeon_combios_get_clock_info()
758 spll->pll_out_min = RBIOS32(pll_info + 0x1e); in radeon_combios_get_clock_info()
759 spll->pll_out_max = RBIOS32(pll_info + 0x22); in radeon_combios_get_clock_info()
762 spll->pll_in_min = RBIOS32(pll_info + 0x48); in radeon_combios_get_clock_info()
763 spll->pll_in_max = RBIOS32(pll_info + 0x4c); in radeon_combios_get_clock_info()
766 spll->pll_in_min = 40; in radeon_combios_get_clock_info()
767 spll->pll_in_max = 500; in radeon_combios_get_clock_info()
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| D | radeon_atombios.c | 1139 struct radeon_pll *spll = &rdev->clock.spll; in radeon_atom_get_clock_info() local
1192 spll->reference_freq = in radeon_atom_get_clock_info()
1195 spll->reference_freq = in radeon_atom_get_clock_info()
1197 spll->reference_div = 0; in radeon_atom_get_clock_info()
1199 spll->pll_out_min = in radeon_atom_get_clock_info()
1201 spll->pll_out_max = in radeon_atom_get_clock_info()
1205 if (spll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1207 spll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1209 spll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1212 spll->pll_in_min = in radeon_atom_get_clock_info()
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| D | rv6xx_dpm.c | 163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
428 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
551 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
840 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
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| D | rv740_dpm.c | 130 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
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| D | rs780_dpm.c | 991 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level()
1013 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk()
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| D | rv730_dpm.c | 49 u32 reference_clock = rdev->clock.spll.reference_freq; in rv730_populate_sclk_value()
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| D | radeon_kms.c | 354 *value = rdev->clock.spll.reference_freq * 10; in radeon_info_ioctl()
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| D | radeon_uvd.c | 958 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; in radeon_uvd_calc_upll_dividers()
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| D | rv770.c | 788 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_get_xclk()
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| D | ci_dpm.c | 1948 u32 ref_clock = rdev->clock.spll.reference_freq; in ci_program_display_gap()
2966 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
3125 u32 reference_clock = rdev->clock.spll.reference_freq; in ci_calculate_sclk_params()
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| D | r600.c | 200 return rdev->clock.spll.reference_freq; in r600_get_xclk()
227 if (rdev->clock.spll.reference_freq == 10000) in r600_set_uvd_clocks()
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| D | rv770_dpm.c | 502 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_populate_sclk_value()
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| /openbsd/src/sys/dev/pci/drm/amd/amdgpu/ |
| D | amdgpu_atomfirmware.c | 708 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atomfirmware_get_clock_info() local
743 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
745 spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
747 spll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
748 spll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
749 spll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
750 spll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
751 spll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
752 spll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
753 spll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
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| D | amdgpu_atombios.c | 570 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atombios_get_clock_info() local
616 spll->reference_freq = in amdgpu_atombios_get_clock_info()
618 spll->reference_div = 0; in amdgpu_atombios_get_clock_info()
620 spll->pll_out_min = in amdgpu_atombios_get_clock_info()
622 spll->pll_out_max = in amdgpu_atombios_get_clock_info()
626 if (spll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
627 spll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
629 spll->pll_in_min = in amdgpu_atombios_get_clock_info()
631 spll->pll_in_max = in amdgpu_atombios_get_clock_info()
634 spll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
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| D | soc24.c | 99 return adev->clock.spll.reference_freq; in soc24_get_xclk()
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| D | amdgpu_si.c | 1469 u32 reference_clock = adev->clock.spll.reference_freq; in si_get_xclk()
1723 unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq; in si_calc_upll_dividers()
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| D | soc21.c | 234 return adev->clock.spll.reference_freq; in soc21_get_xclk()
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| D | nv.c | 313 return adev->clock.spll.reference_freq; in nv_get_xclk()
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| D | soc15.c | 325 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
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| D | amdgpu_cik.c | 919 u32 reference_clock = adev->clock.spll.reference_freq; in cik_get_xclk()
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| D | amdgpu.h | 424 struct amdgpu_pll spll; member
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| D | vi.c | 542 u32 reference_clock = adev->clock.spll.reference_freq; in vi_get_xclk()
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| /openbsd/src/sys/dev/pci/drm/i915/display/ |
| D | intel_dpll_mgr.h | 200 u32 spll; member
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| D | intel_dpll_mgr.c | 706 intel_de_write(i915, SPLL_CTL, hw_state->spll); in hsw_ddi_spll_enable()
779 hw_state->spll = val; in hsw_ddi_spll_get_hw_state()
1153 hw_state->spll = in hsw_ddi_spll_compute_dpll()
1177 switch (hw_state->spll & SPLL_FREQ_MASK) { in hsw_ddi_spll_get_freq()
1254 hw_state->wrpll, hw_state->spll); in hsw_dump_hw_state()
1264 a->spll == b->spll; in hsw_compare_hw_state()
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