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/openbsd/src/gnu/llvm/libcxx/include/experimental/
Dsimd14 experimental/simd synopsis
37 // traits [simd.traits]
61 // class template simd [simd.class]
62 template <class T, class Abi = simd_abi::compatible<T>> class simd;
63 template <class T> using native_simd = simd<T, simd_abi::native<T>>;
64 template <class T, int N> using fixed_size_simd = simd<T, simd_abi::fixed_size<N>>;
66 // class template simd_mask [simd.mask.class]
71 // casts [simd.casts]
72 template <class T, class U, class Abi> see below simd_cast(const simd<U, Abi>&);
73 template <class T, class U, class Abi> see below static_simd_cast(const simd<U, Abi>&);
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/openbsd/src/gnu/llvm/clang/include/clang/Basic/
DBuiltinsWebAssembly.def165 TARGET_BUILTIN(__builtin_wasm_relaxed_madd_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd")
166 TARGET_BUILTIN(__builtin_wasm_relaxed_nmadd_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd")
167 TARGET_BUILTIN(__builtin_wasm_relaxed_madd_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
168 TARGET_BUILTIN(__builtin_wasm_relaxed_nmadd_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
170 TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "relaxed-simd…
171 TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i16x8, "V8sV8sV8sV8s", "nc", "relaxed-simd")
172 TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i32x4, "V4iV4iV4iV4i", "nc", "relaxed-simd")
173 TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "relaxed-simd…
175 TARGET_BUILTIN(__builtin_wasm_relaxed_swizzle_i8x16, "V16ScV16ScV16Sc", "nc", "relaxed-simd")
177 TARGET_BUILTIN(__builtin_wasm_relaxed_min_f32x4, "V4fV4fV4f", "nc", "relaxed-simd")
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DOpenMPKinds.def94 OPENMP_SCHEDULE_MODIFIER(simd)
/openbsd/src/gnu/llvm/llvm/include/llvm/Frontend/OpenMP/
DOMP.td226 def OMPC_Simd : Clause<"simd"> { let clangClass = "OMPSIMDClause"; }
485 def OMP_Simd : Directive<"simd"> {
861 def OMP_ParallelForSimd : Directive<"parallel for simd"> {
885 def OMP_ParallelDoSimd : Directive<"parallel do simd"> {
957 def OMP_ForSimd : Directive<"for simd"> {
977 def OMP_DoSimd : Directive<"do simd"> {
1002 def OMP_DeclareSimd : Directive<"declare simd"> {
1041 def OMP_TaskLoopSimd : Directive<"taskloop simd"> {
1142 def OMP_DistributeParallelForSimd : Directive<"distribute parallel for simd"> {
1166 def OMP_DistributeParallelDoSimd : Directive<"distribute parallel do simd"> {
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/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v9_4_2.c422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
437 for (simd = 0; simd < SIMD_ID_MAX; simd++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
467 for (simd = 0; simd < SIMD_ID_MAX; simd++) in gfx_v9_4_2_wait_for_waves_assigned()
1804 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1808 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1818 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local
1829 simd = i / cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
1832 wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_2_log_cu_timeout_status()
1833 wave_pc_lo = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_2_log_cu_timeout_status()
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Dgfx_v6_0.c2945 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2949 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2955 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
2961 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
2970 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v6_0_read_wave_data() argument
2974 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data()
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Dgfx_v7_0.c4049 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4053 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
4059 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
4065 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
4074 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v7_0_read_wave_data() argument
4078 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4079 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4080 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4081 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4082 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
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Damdgpu_umr.h50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
Damdgpu_debugfs.c434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
1061 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
1072 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; in amdgpu_debugfs_wave_read()
1092 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
1153 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
1164 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; in amdgpu_debugfs_gpr_read()
1186 adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1189 adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
Damdgpu_gfx.h292 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
294 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
297 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
Dgfx_v9_4_3.c725 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t … in wave_read_ind() argument
729 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
735 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in wave_read_regs() argument
741 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
751 uint32_t xcc_id, uint32_t simd, uint32_t wave, in gfx_v9_4_3_read_wave_data() argument
756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_read_wave_data()
757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_3_read_wave_data()
758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_4_3_read_wave_data()
759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_3_read_wave_data()
760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_3_read_wave_data()
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Dgfx_v8_0.c5196 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5200 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
5206 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
5212 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
5221 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v8_0_read_wave_data() argument
5225 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5226 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5227 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5228 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5229 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
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Dgfx_v9_0.c1918 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1922 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1928 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
1934 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
1943 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v9_0_read_wave_data() argument
1947 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
1948 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
1949 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
1950 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
1951 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
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/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/
DWebAssembly.td28 def FeatureRelaxedSIMD : SubtargetFeature<"relaxed-simd", "SIMDLevel", "RelaxedSIMD",
29 "Enable relaxed-simd instructions">;
DWebAssemblyInstrInfo.td31 AssemblerPredicate<(all_of FeatureRelaxedSIMD), "relaxed-simd">;
/openbsd/src/regress/lib/libcrypto/x509/bettertls/certificates/
D1100.crt20 C0e0o8C8F503GbOunHOUyQpWpb0/simd+lj2L3ZhubPvcY8tHjj0OUf7Mygq6QGK
/openbsd/src/gnu/llvm/llvm/docs/AMDGPU/
Dgfx8_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
Dgfx7_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
Dgfx9_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
Dgfx90a_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
Dgfx11_hwreg.rst50 HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
Dgfx1030_hwreg.rst50 HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
Dgfx10_hwreg.rst50 HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
Dgfx940_hwreg.rst50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
/openbsd/src/gnu/llvm/clang/docs/
DOpenMPSupport.rst22 * #pragma omp declare simd: :part:`Partial`. We support parsing/semantic
161 | task | master taskloop simd | :go…
163 | task | parallel master taskloop simd | :go…
165 | SIMD | atomic and simd constructs inside SIMD code | :go…

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