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Searched refs:res_pool (Results 1 – 25 of 33) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/amd/display/dc/core/
Ddc_link_enc_cfg.c40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
159 stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx]; in add_link_enc_assignment()
180 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
189 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
255 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA]; in get_link_enc_used_by_link()
274 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
275 if (dc->res_pool->link_encoders[i]) in clear_enc_assignments()
313 dc->res_pool->funcs->link_enc_unassign(state, dc->current_state->streams[i]); in link_enc_cfg_link_encs_assign()
526 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA]; in link_enc_cfg_get_link_enc_used_by_link()
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Damdgpu_dc.c242 for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) { in create_links()
314 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in create_link_encoders()
315 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in create_link_encoders()
328 if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) { in create_link_encoders()
330 struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; in create_link_encoders()
332 if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) { in create_link_encoders()
333 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx, in create_link_encoders()
336 dc->res_pool->link_encoders[i] = link_enc; in create_link_encoders()
337 dc->res_pool->dig_link_enc_count++; in create_link_encoders()
358 if (!dc->res_pool) in destroy_link_encoders()
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Ddc_resource.c224 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
229 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
233 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
237 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
242 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
246 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
250 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
254 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
258 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
264 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
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Ddc_state.c304 if (dc->res_pool) in dc_state_construct()
388 if (state->stream_count >= dc->res_pool->timing_generator_count) { in dc_state_add_stream()
398 state, dc->res_pool, stream); in dc_state_add_stream()
423 dc->current_state, dc->res_pool, stream, 1); in dc_state_remove_stream()
425 state, dc->res_pool, stream); in dc_state_remove_stream()
463 new_ctx, cur_ctx, dc->res_pool, in remove_mpc_combine_for_stream()
473 struct resource_pool *pool = dc->res_pool; in dc_state_add_plane()
513 dc->current_state, dc->res_pool, stream, in dc_state_add_plane()
543 struct resource_pool *pool = dc->res_pool; in dc_state_remove_plane()
924 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_state_remove_phantom_streams_and_planes()
Ddc_link_exports.c149 if (dc->res_pool->oem_device) in dc_is_oem_i2c_device_present()
151 dc->res_pool, in dc_is_oem_i2c_device_present()
152 dc->res_pool->oem_device, in dc_is_oem_i2c_device_present()
168 dc->res_pool, in dc_submit_i2c()
177 struct ddc_service *ddc = dc->res_pool->oem_device; in dc_submit_i2c_oem()
181 dc->res_pool, in dc_submit_i2c_oem()
Ddc_surface.c73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
139 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
154 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
Ddc_hw_sequencer.c530 for (int i = 0; i < dc->res_pool->pipe_count; i++) { in set_p_state_switch_method()
702 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc; in hwss_build_fast_sequence()
709 block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc; in hwss_build_fast_sequence()
716 block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc; in hwss_build_fast_sequence()
1066 int opp_count = dc->res_pool->res_cap->num_opp; in hwss_wait_for_outstanding_hw_updates()
1071 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { in hwss_wait_for_outstanding_hw_updates()
1087 if ((dc->res_pool->opps[opp_inst] != NULL) && in hwss_wait_for_outstanding_hw_updates()
1088 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) { in hwss_wait_for_outstanding_hw_updates()
1089 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); in hwss_wait_for_outstanding_hw_updates()
1090 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; in hwss_wait_for_outstanding_hw_updates()
Ddc_stream.c202 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign) in dc_copy_stream()
427 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_stream_program_cursor_position()
483 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
504 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
516 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
534 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
606 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_remove_writeback()
786 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { in dc_stream_add_dsc_to_resource()
787 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); in dc_stream_add_dsc_to_resource()
Ddc_debug.c316 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in context_timing_trace()
320 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
332 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/
Ddc_edid_parser.c35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
Ddc_dmub_srv.c414 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dc_dmub_srv_populate_fams_pipe_info()
446 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_srv_p_state_delegate()
465 for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { in dc_dmub_srv_p_state_delegate()
651 for (i = 0; i < dc->res_pool->pipe_count; i++) { in populate_subvp_cmd_vblank_pipe_info()
827 for (j = 0; j < dc->res_pool->pipe_count; j++) { in populate_subvp_cmd_pipe_info()
874 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_setup_subvp_dmub_command()
887 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_setup_subvp_dmub_command()
921 (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; in dc_dmub_setup_subvp_dmub_command()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer_debug.c81 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
85 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
113 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
119 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
191 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
233 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
290 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
330 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
385 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
416 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c57 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce60_should_enable_fbc()
70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
Ddcn20_fpu.c998 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
1049 for (i = 0; i < dc->res_pool->pipe_count; i++) { in is_dtbclk_required()
1064 for (i = 0; i < dc->res_pool->pipe_count; i++) { in decide_zstate_support()
1152 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); in dcn20_calculate_dlg_params()
1180 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1225 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1326 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1350 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1368 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_populate_dml_pipes_from_context()
1726 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn20_populate_dml_pipes_from_context()
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/openbsd/src/sys/dev/pci/drm/amd/display/modules/power/
Dpower_helpers.c692 bool dmub_init_abm_config(struct resource_pool *res_pool, in dmub_init_abm_config() argument
702 if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) in dmub_init_abm_config()
756 if (res_pool->multiple_abms[inst]) { in dmub_init_abm_config()
757 result = res_pool->multiple_abms[inst]->funcs->init_abm_config( in dmub_init_abm_config()
758 res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); in dmub_init_abm_config()
760 result = res_pool->abm->funcs->init_abm_config( in dmub_init_abm_config()
761 res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); in dmub_init_abm_config()
Dpower_helpers.h52 bool dmub_init_abm_config(struct resource_pool *res_pool,
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.c76 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_clock()
129 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_dispclk()
/openbsd/src/sys/dev/pci/drm/amd/display/amdgpu_dm/
Damdgpu_dm_mst_types.c848 params[i].sink->ctx->dc->res_pool->dscs[0], in set_dsc_configs_from_fairness_vars()
901 param.sink->ctx->dc->res_pool->dscs[0], in bpp_x16_from_pbn()
1170 stream->sink->ctx->dc->res_pool->dscs[0], in compute_mst_dsc_configs_for_link()
1413 struct resource_pool *res_pool; in compute_mst_dsc_configs_for_state() local
1422 res_pool = stream->ctx->dc->res_pool; in compute_mst_dsc_configs_for_state()
1441 if (res_pool->funcs->remove_stream_from_ctx && in compute_mst_dsc_configs_for_state()
1442 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) in compute_mst_dsc_configs_for_state()
1705 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], in is_dsc_common_config_possible()
1849 if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0], in dm_dp_mst_is_port_support_mode()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dce/
Ddce_aux.c443 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_configure_timeout()
577 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_transfer_raw()
623 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_transfer_dmub_raw()
716 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_transfer_with_retries()
Ddce_clk_mgr.c254 struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; in dce_set_clock()
294 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dce112_set_clock()
654 pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr_vbios_smu.c129 struct dmcu *dmcu = dc->res_pool->dmcu; in rv1_vbios_smu_set_dispclk()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr_vbios_smu.c147 struct dmcu *dmcu = dc->res_pool->dmcu; in rn_vbios_smu_set_dispclk()
Drn_clk_mgr.c113 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in rn_update_clocks_update_dpp_dto()
119 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst; in rn_update_clocks_update_dpp_dto()
143 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in rn_update_clocks()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c205 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn3_update_clocks()
424 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( in dcn3_get_memclk_states_from_smu()

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