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/openbsd/src/gnu/llvm/compiler-rt/lib/sanitizer_common/
Dsanitizer_syscall_linux_loongarch64.inc14 // About local register variables:
31 register u64 a7 asm("$a7") = nr;
32 register u64 a0 asm("$a0");
42 register u64 a7 asm("$a7") = nr;
43 register u64 a0 asm("$a0") = arg1;
53 register u64 a7 asm("$a7") = nr;
54 register u64 a0 asm("$a0") = arg1;
55 register u64 a1 asm("$a1") = arg2;
66 register u64 a7 asm("$a7") = nr;
67 register u64 a0 asm("$a0") = arg1;
[all …]
Dsanitizer_syscall_linux_aarch64.inc16 register u64 x8 asm("x8") = nr;
17 register u64 x0 asm("x0");
28 register u64 x8 asm("x8") = nr;
29 register u64 x0 asm("x0") = arg1;
40 register u64 x8 asm("x8") = nr;
41 register u64 x0 asm("x0") = arg1;
42 register u64 x1 asm("x1") = arg2;
53 register u64 x8 asm("x8") = nr;
54 register u64 x0 asm("x0") = arg1;
55 register u64 x1 asm("x1") = arg2;
[all …]
Dsanitizer_syscall_linux_arm.inc16 register u32 r8 asm("r7") = nr;
17 register u32 r0 asm("r0");
28 register u32 r8 asm("r7") = nr;
29 register u32 r0 asm("r0") = arg1;
40 register u32 r8 asm("r7") = nr;
41 register u32 r0 asm("r0") = arg1;
42 register u32 r1 asm("r1") = arg2;
53 register u32 r8 asm("r7") = nr;
54 register u32 r0 asm("r0") = arg1;
55 register u32 r1 asm("r1") = arg2;
[all …]
Dsanitizer_syscall_linux_hexagon.inc37 register u32 r6 __asm__("r6") = n;
38 register u32 r0 __asm__("r0");
45 register u32 r6 __asm__("r6") = n;
46 register u32 r0 __asm__("r0") = a;
54 register u32 r6 __asm__("r6") = n;
55 register u32 r0 __asm__("r0") = a;
56 register u32 r1 __asm__("r1") = b;
64 register u32 r6 __asm__("r6") = n;
65 register u32 r0 __asm__("r0") = a;
66 register u32 r1 __asm__("r1") = b;
[all …]
Dsanitizer_syscall_linux_riscv64.inc13 // About local register variables:
34 register u64 a7 asm("a7") = nr;
35 register u64 a0 asm("a0");
45 register u64 a7 asm("a7") = nr;
46 register u64 a0 asm("a0") = arg1;
56 register u64 a7 asm("a7") = nr;
57 register u64 a0 asm("a0") = arg1;
58 register u64 a1 asm("a1") = arg2;
69 register u64 a7 asm("a7") = nr;
70 register u64 a0 asm("a0") = arg1;
[all …]
/openbsd/src/gnu/usr.bin/binutils/gas/doc/
Dc-v850.texi98 @cindex V850 register names
99 @cindex register names, V850
102 @cindex @code{zero} register, V850
103 @item general register 0
105 @item general register 1
107 @item general register 2
109 @cindex @code{sp} register, V850
110 @item general register 3
112 @cindex @code{gp} register, V850
113 @item general register 4
[all …]
/openbsd/src/gnu/usr.bin/binutils-2.17/gas/doc/
Dc-v850.texi98 @cindex V850 register names
99 @cindex register names, V850
102 @cindex @code{zero} register, V850
103 @item general register 0
105 @item general register 1
107 @item general register 2
109 @cindex @code{sp} register, V850
110 @item general register 3
112 @cindex @code{gp} register, V850
113 @item general register 4
[all …]
/openbsd/src/sys/dev/microcode/aic7xxx/
Daic79xx.reg3 * Aic79xx register and scratch ram definitions.
86 * as the source and destination of any register accesses in our
87 * register window.
89 register MODE_PTR {
103 register INTSTAT {
120 register SEQINTCODE {
199 register CLRINT {
215 register ERROR {
230 register CLRERR {
246 register HCNTRL {
[all …]
Daic7xxx.reg3 * Aic7xxx register and scratch ram definitions.
58 register SCSISEQ {
75 register SXFRCTL0 {
91 register SXFRCTL1 {
107 register SCSISIGI {
134 * Writing to this register modifies the control signals on the bus. Only
138 register SCSISIGO {
163 * Contents of this register determine the Synchronous SCSI data transfer
168 register SCSIRATE {
184 register SCSIID {
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/openbsd/src/gnu/llvm/llvm/docs/AMDGPU/
Dgfx10_hwreg.rst13 Bits of a hardware register being accessed.
33 hwreg({0..63}) All bits of a register indicated by the register *id*.
34 hwreg(<*name*>) All bits of a register indicated by the register *name*.
35 …hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offs…
36 …hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *of…
42 Predefined register *names* include:
56 HW_REG_TBA_LO tba_lo register.
57 HW_REG_TBA_HI tba_hi register.
58 HW_REG_TMA_LO tma_lo register.
59 HW_REG_TMA_HI tma_hi register.
[all …]
Dgfx1030_hwreg.rst13 Bits of a hardware register being accessed.
33 hwreg({0..63}) All bits of a register indicated by the register *id*.
34 hwreg(<*name*>) All bits of a register indicated by the register *name*.
35 …hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offs…
36 …hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *of…
42 Predefined register *names* include:
56 HW_REG_TBA_LO tba_lo register.
57 HW_REG_TBA_HI tba_hi register.
58 HW_REG_TMA_LO tma_lo register.
59 HW_REG_TMA_HI tma_hi register.
[all …]
Dgfx9_hwreg.rst13 Bits of a hardware register being accessed.
33 hwreg({0..63}) All bits of a register indicated by the register *id*.
34 hwreg(<*name*>) All bits of a register indicated by the register *name*.
35 …hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offs…
36 …hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *of…
42 Predefined register *names* include:
55 HW_REG_TBA_LO tba_lo register.
56 HW_REG_TBA_HI tba_hi register.
57 HW_REG_TMA_LO tma_lo register.
58 HW_REG_TMA_HI tma_hi register.
Dgfx90a_hwreg.rst13 Bits of a hardware register being accessed.
33 hwreg({0..63}) All bits of a register indicated by the register *id*.
34 hwreg(<*name*>) All bits of a register indicated by the register *name*.
35 …hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offs…
36 …hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *of…
42 Predefined register *names* include:
55 HW_REG_TBA_LO tba_lo register.
56 HW_REG_TBA_HI tba_hi register.
57 HW_REG_TMA_LO tma_lo register.
58 HW_REG_TMA_HI tma_hi register.
Dgfx940_hwreg.rst13 Bits of a hardware register being accessed.
33 hwreg({0..63}) All bits of a register indicated by the register *id*.
34 hwreg(<*name*>) All bits of a register indicated by the register *name*.
35 …hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offs…
36 …hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *of…
42 Predefined register *names* include:
55 HW_REG_TBA_LO tba_lo register.
56 HW_REG_TBA_HI tba_hi register.
57 HW_REG_TMA_LO tma_lo register.
58 HW_REG_TMA_HI tma_hi register.
Dgfx11_hwreg.rst13 Bits of a hardware register being accessed.
33 hwreg({0..63}) All bits of a register indicated by the register *id*.
34 hwreg(<*name*>) All bits of a register indicated by the register *name*.
35 …hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offs…
36 …hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *of…
42 Predefined register *names* include:
56 HW_REG_FLAT_SCR_LO flat_scratch_lo register.
57 HW_REG_FLAT_SCR_HI flat_scratch_hi register.
Dgfx8_hwreg.rst13 Bits of a hardware register being accessed.
33 hwreg({0..63}) All bits of a register indicated by the register *id*.
34 hwreg(<*name*>) All bits of a register indicated by the register *name*.
35 …hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offs…
36 …hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *of…
42 Predefined register *names* include:
Dgfx7_hwreg.rst13 Bits of a hardware register being accessed.
33 hwreg({0..63}) All bits of a register indicated by the register *id*.
34 hwreg(<*name*>) All bits of a register indicated by the register *name*.
35 …hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offs…
36 …hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *of…
42 Predefined register *names* include:
/openbsd/src/gnu/gcc/gcc/config/i386/
Dconstraints.md25 ;; Integer register constraints.
28 "Legacy register---the eight integer registers available on all
33 "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
34 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
37 "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
41 "@internal Any register that can be used as the index in a base+index
42 memory access: that is, any general register except the stack pointer.")
45 "The @code{a} register.")
48 "The @code{b} register.")
51 "The @code{c} register.")
[all …]
/openbsd/src/gnu/gcc/gcc/config/iq2000/
Dabi38 %4 argument register 1
39 %5 argument register 2
40 %6 argument register 3
41 %7 argument register 4
42 %8 argument register 5
43 %9 argument register 6
44 %10 argument register 7
45 %11 argument register 8
126 general-purpose register. STARG is the address of the next available stack
142 general-purpose register,
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMScheduleA8.td123 // Scaled register offset, issues over 2 cycles
144 // Scaled register offset with update, issues over 2 cycles
202 // Scaled register offset, issues over 2 cycles
222 // Scaled register offset with update, issues over 2 cycles
774 // Double-register FP Unary
778 // Quad-register FP Unary
784 // Double-register FP Binary
792 // Double-register FP VMUL
797 // Quad-register FP Binary
803 // Quad-register FP VMUL
[all …]
/openbsd/src/gnu/gcc/gcc/config/mt/
DABI.txt43 r1 argument register 1
44 r2 argument register 2
45 r3 argument register 3
46 r4 argument register 4
118 general-purpose register. STARG is the address of the next available stack
134 general-purpose register,
136 * A struct or union small enough to fit in a register (<= 32 bits)
142 general-purpose register GR and advance GR to the next general-purpose
143 register. Values shorter than the register size are sign-extended or
150 next register. Load the 64-bit long long or double value into register
[all …]
/openbsd/src/gnu/llvm/llvm/docs/
DAMDGPUOperandSyntax.rst39 **v**\<N> A single 32-bit *vector* register.
43 **v[**\ <N>\ **]** A single 32-bit *vector* register.
68 (first register must be even).
95 Each register may be specified using the syntax
100 consecutive indices. Moreover, the same register
121 16-bit vector registers. Each :ref:`32-bit vector register<amdgpu_synid_v>` is divided into two 16-…
132 … **v**\<N> A single 16-bit *vector* register (low half).
159 … **acc**\<N> A single 32-bit *accumulator* register.
163 … **acc[**\ <N>\ **]** A single 32-bit *accumulator* register.
188 (first register must be even).
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/
DWebAssemblyRegisterInfo.td10 /// This file describes the WebAssembly register classes and some nominal
35 // The register allocation framework requires register classes have at least
36 // one register, so we define a few for the integer / floating point register
37 // classes since we otherwise don't need a physical register in those classes.
49 // The value stack "register". This is an opaque entity which serves to order
53 // The incoming arguments "register". This is an opaque entity which serves to
/openbsd/src/gnu/gcc/gcc/config/s390/
Dconstraints.md27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
57 ;; Q -- Memory reference without index register and with short displacement.
58 ;; R -- Memory reference with index register and short displacement.
59 ;; S -- Memory reference without index register but with long displacement.
60 ;; T -- Memory reference with index register and long displacement.
78 "Any address register from 1 to 15.")
83 "Condition code register 33")
88 "Any register from 0 to 15")
[all …]
/openbsd/src/gnu/usr.bin/binutils-2.17/cpu/
Dsh.cpu124 (type register DI (64))
140 (type register SI (16))
154 (type register DI (64))
168 (comment "Status register")
170 (type register SI)
175 (comment "Floating point status and control register")
177 (type register SI)
182 (comment "Floating point register file bit")
184 (type register BI)
193 (type register BI)
[all …]

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