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Searched refs:regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_12_0_0_offset.h2445 #define regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX … macro
Dgc_11_0_0_offset.h6469 #define regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX … macro