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Searched refs:regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_12_0_0_offset.h1661 #define regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX … macro
Dgc_11_0_3_offset.h1511 #define regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX … macro
Dgc_11_0_0_offset.h1499 #define regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX … macro