Home
last modified time | relevance | path

Searched refs:regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h506 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX … macro
Dgc_12_0_0_offset.h515 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX … macro
Dgc_11_0_3_offset.h507 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX … macro
Dgc_11_0_0_offset.h501 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX … macro