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Searched refs:regSDMA0_QUEUE2_RB_WPTR (Results 1 – 6 of 6) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dsdma_v7_0.c104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),
Dsdma_v6_0.c104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h377 #define regSDMA0_QUEUE2_RB_WPTR … macro
Dgc_12_0_0_offset.h380 #define regSDMA0_QUEUE2_RB_WPTR … macro
Dgc_11_0_3_offset.h378 #define regSDMA0_QUEUE2_RB_WPTR … macro
Dgc_11_0_0_offset.h372 #define regSDMA0_QUEUE2_RB_WPTR … macro