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Searched refs:regSDMA0_QUEUE0_RB_BASE_HI (Results 1 – 7 of 7) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v11.c399 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_BASE_HI, in hqd_sdma_load_v11()
Dsdma_v7_0.c556 …WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr … in sdma_v7_0_gfx_resume()
Dsdma_v6_0.c532 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr … in sdma_v6_0_gfx_resume()
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h199 #define regSDMA0_QUEUE0_RB_BASE_HI … macro
Dgc_12_0_0_offset.h186 #define regSDMA0_QUEUE0_RB_BASE_HI … macro
Dgc_11_0_3_offset.h200 #define regSDMA0_QUEUE0_RB_BASE_HI … macro
Dgc_11_0_0_offset.h194 #define regSDMA0_QUEUE0_RB_BASE_HI … macro