Home
last modified time | relevance | path

Searched refs:regRLC_SPARE_INT_0 (Results 1 – 6 of 6) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h9031 #define regRLC_SPARE_INT_0 … macro
Dgc_12_0_0_offset.h7041 #define regRLC_SPARE_INT_0 … macro
Dgc_11_0_3_offset.h11220 #define regRLC_SPARE_INT_0 … macro
Dgc_11_0_0_offset.h10600 #define regRLC_SPARE_INT_0 … macro
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v12_0.c702 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v12_0_init_rlcg_reg_access_ctrl()
Dgfx_v11_0.c876 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()