Home
last modified time | relevance | path

Searched refs:regRLC_MEM_SLP_CNTL (Results 1 – 7 of 7) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v9_4_3.c2626 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2629 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2652 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2655 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2819 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); in gfx_v9_4_3_get_clockgating_state()
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_4_3_offset.h6400 #define regRLC_MEM_SLP_CNTL … macro
Dgc_9_4_2_offset.h4894 #define regRLC_MEM_SLP_CNTL … macro
Dgc_11_5_0_offset.h8953 #define regRLC_MEM_SLP_CNTL … macro
Dgc_12_0_0_offset.h6762 #define regRLC_MEM_SLP_CNTL … macro
Dgc_11_0_3_offset.h10914 #define regRLC_MEM_SLP_CNTL … macro
Dgc_11_0_0_offset.h10302 #define regRLC_MEM_SLP_CNTL … macro