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Searched refs:regRLC_CGCG_CGLS_CTRL (Results 1 – 9 of 9) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v9_4_3.c1618 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); in gfx_v9_4_3_xcc_rlc_resume()
2688 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2697 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2706 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2711 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2810 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); in gfx_v9_4_3_get_clockgating_state()
Dgfx_v12_0.c1948 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v12_0_rlc_resume()
3899 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
3914 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
3963 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
3972 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4144 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_get_clockgating_state()
Dgfx_v11_0.c2285 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v11_0_rlc_resume()
5194 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5209 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5258 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5267 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5488 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_get_clockgating_state()
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_4_3_offset.h6488 #define regRLC_CGCG_CGLS_CTRL … macro
Dgc_9_4_2_offset.h4976 #define regRLC_CGCG_CGLS_CTRL … macro
Dgc_11_5_0_offset.h8569 #define regRLC_CGCG_CGLS_CTRL … macro
Dgc_12_0_0_offset.h6400 #define regRLC_CGCG_CGLS_CTRL … macro
Dgc_11_0_3_offset.h10500 #define regRLC_CGCG_CGLS_CTRL … macro
Dgc_11_0_0_offset.h9898 #define regRLC_CGCG_CGLS_CTRL … macro