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Searched refs:regGCVM_L2_CNTL2 (Results 1 – 11 of 11) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dimu_v11_0.c221 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0xe0000000),
304 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0xe0000000),
Dgfxhub_v3_0_3.c233 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); in gfxhub_v3_0_3_init_cache_regs()
236 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v3_0_3_init_cache_regs()
Dimu_v11_0_3.c84 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0xe0000000),
Dgfxhub_v12_0.c236 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); in gfxhub_v12_0_init_cache_regs()
239 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v12_0_init_cache_regs()
Dgfxhub_v11_5_0.c231 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); in gfxhub_v11_5_0_init_cache_regs()
234 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v11_5_0_init_cache_regs()
Dgfxhub_v3_0.c228 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); in gfxhub_v3_0_init_cache_regs()
231 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v3_0_init_cache_regs()
Dimu_v12_0.c242 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0x1c0000),
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h1861 #define regGCVM_L2_CNTL2 … macro
Dgc_12_0_0_offset.h2768 #define regGCVM_L2_CNTL2 … macro
Dgc_11_0_3_offset.h2874 #define regGCVM_L2_CNTL2 … macro
Dgc_11_0_0_offset.h2732 #define regGCVM_L2_CNTL2 … macro