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Searched refs:regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT (Results 1 – 6 of 6) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h3691 #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT … macro
Dgc_12_0_0_offset.h3958 #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT … macro
Dgc_11_0_3_offset.h4942 #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT … macro
Dgc_11_0_0_offset.h4718 #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT … macro
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v12_0.c171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
Dgfx_v11_0.c211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),