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Searched refs:regCP_HQD_EOP_WPTR_MEM (Results 1 – 9 of 9) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_4_3_offset.h3390 #define regCP_HQD_EOP_WPTR_MEM … macro
Dgc_9_4_2_offset.h801 #define regCP_HQD_EOP_WPTR_MEM … macro
Dgc_11_5_0_offset.h3681 #define regCP_HQD_EOP_WPTR_MEM … macro
Dgc_12_0_0_offset.h3948 #define regCP_HQD_EOP_WPTR_MEM … macro
Dgc_11_0_3_offset.h4932 #define regCP_HQD_EOP_WPTR_MEM … macro
Dgc_11_0_0_offset.h4708 #define regCP_HQD_EOP_WPTR_MEM … macro
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v9_4_3.c155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
Dgfx_v12_0.c167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
Dgfx_v11_0.c207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),