Searched refs:queue_mask (Results 1 – 12 of 12) sorted by relevance
| /openbsd/src/sys/dev/pci/drm/amd/amdkfd/ |
| D | kfd_packet_manager_vi.c | 136 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()
137 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_vi()
|
| D | kfd_packet_manager_v9.c | 212 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_v9()
213 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_v9()
|
| D | kfd_device_queue_manager.c | 1679 res.queue_mask = 0; in set_sched_resources()
1695 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { in set_sched_resources()
1700 res.queue_mask |= 1ull in set_sched_resources()
1710 res.vmid_mask, res.queue_mask); in set_sched_resources()
|
| D | kfd_priv.h | 636 uint64_t queue_mask; member
|
| /openbsd/src/sys/dev/pci/drm/amd/amdgpu/ |
| D | amdgpu_gfx.c | 639 uint64_t queue_mask = ~0ULL; in amdgpu_gfx_mes_enable_kcq() local
653 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); in amdgpu_gfx_mes_enable_kcq()
677 uint64_t queue_mask = 0; in amdgpu_gfx_enable_kcq() local
693 if (WARN_ON(i > (sizeof(queue_mask)*8))) { in amdgpu_gfx_enable_kcq()
698 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i)); in amdgpu_gfx_enable_kcq()
716 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); in amdgpu_gfx_enable_kcq()
|
| D | amdgpu_gfx.h | 128 uint64_t queue_mask);
|
| D | gfx_v8_0.c | 4315 uint64_t queue_mask = 0; in gfx_v8_0_kiq_kcq_enable() local
4325 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { in gfx_v8_0_kiq_kcq_enable()
4330 queue_mask |= (1ull << i); in gfx_v8_0_kiq_kcq_enable()
4341 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v8_0_kiq_kcq_enable()
4342 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v8_0_kiq_kcq_enable()
|
| D | gfx_v9_4_3.c | 173 uint64_t queue_mask) in gfx_v9_4_3_kiq_set_resources() argument
187 lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v9_4_3_kiq_set_resources()
189 upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v9_4_3_kiq_set_resources()
|
| D | gfx_v12_0.c | 246 uint64_t queue_mask) in gfx_v12_0_kiq_set_resources() argument
251 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v12_0_kiq_set_resources()
252 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v12_0_kiq_set_resources()
|
| D | gfx_v9_0.c | 901 uint64_t queue_mask) in gfx_v9_0_kiq_set_resources() argument
915 lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v9_0_kiq_set_resources()
917 upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v9_0_kiq_set_resources()
|
| D | gfx_v11_0.c | 294 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) in gfx11_kiq_set_resources() argument
300 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx11_kiq_set_resources()
301 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx11_kiq_set_resources()
|
| D | gfx_v10_0.c | 3678 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) in gfx10_kiq_set_resources() argument
3683 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()
3684 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
|