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Searched refs:plane_res (Results 1 – 18 of 18) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c151 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in dce60_set_default_colors()
158 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in dce60_set_default_colors()
160 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( in dce60_set_default_colors()
161 pipe_ctx->plane_res.xfm, &default_adjust); in dce60_set_default_colors()
202 switch (pipe_ctx->plane_res.scl_data.format) { in dce60_get_surface_visual_confirm_color()
246 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in dce60_program_scaler()
247 pipe_ctx->plane_res.xfm, in dce60_program_scaler()
248 pipe_ctx->plane_res.scl_data.lb_params.depth, in dce60_program_scaler()
265 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/core/
Ddc_resource.c931 if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp) in calculate_adjust_recout_for_visual_confirm()
935 *dpp_offset *= pipe_ctx->plane_res.dpp->inst; in calculate_adjust_recout_for_visual_confirm()
1102 pipe_ctx->plane_res.scl_data.recout = shift_rec( in calculate_recout()
1106 &pipe_ctx->plane_res.scl_data.recout, in calculate_recout()
1110 memset(&pipe_ctx->plane_res.scl_data.recout, 0, in calculate_recout()
1131 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1134 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1139 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
1141 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
1143 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
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Ddc_stream.c351 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
353 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in program_cursor_position()
354 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in program_cursor_position()
445 pipe_ctx->plane_res.hubp->mpcc_id); in dc_stream_program_cursor_position()
764 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
Ddc_surface.c76 if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) in dc_plane_get_pipe_mask()
77 pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst; in dc_plane_get_pipe_mask()
Ddc_hw_sequencer.c336 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
393 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color()
703 …ce[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; in hwss_build_fast_sequence()
881 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_setup_dpp()
907 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_program_bias_and_scale()
1080 hubp = pipe_ctx->plane_res.hubp; in hwss_wait_for_outstanding_hw_updates()
Damdgpu_dc.c781 if (pipes->plane_res.xfm && in dc_stream_set_dither_option()
782 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) { in dc_stream_set_dither_option()
783 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in dc_stream_set_dither_option()
784 pipes->plane_res.xfm, in dc_stream_set_dither_option()
785 pipes->plane_res.scl_data.lb_params.depth, in dc_stream_set_dither_option()
2214 mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; in dc_acquire_release_mpc_3dlut()
3913 pipe_ctx->plane_res.hubp->inst); in commit_planes_for_stream()
3981 cur_pipe->plane_res.hubp->funcs->validate_dml_output( in commit_planes_for_stream()
3982 cur_pipe->plane_res.hubp, dc->ctx, in commit_planes_for_stream()
5427 hubp = pipe->plane_res.hubp; in blank_and_force_memclk()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/
Ddc_spl_translate.c91 spl_in->basic_in.format = (enum spl_pixel_format)pipe_ctx->plane_res.scl_data.format; in translate_SPL_in_params_from_pipe_ctx()
130 spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en; in translate_SPL_in_params_from_pipe_ctx()
187 spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; in translate_SPL_in_params_from_pipe_ctx()
188 spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; in translate_SPL_in_params_from_pipe_ctx()
208 populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout); in translate_SPL_out_params_to_pipe_ctx()
210 …populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->rat… in translate_SPL_out_params_to_pipe_ctx()
212 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewp… in translate_SPL_out_params_to_pipe_ctx()
214 …populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->vie… in translate_SPL_out_params_to_pipe_ctx()
216 populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps); in translate_SPL_out_params_to_pipe_ctx()
218 populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init); in translate_SPL_out_params_to_pipe_ctx()
Ddc_trace.h31 pipe_ctx->stream, &pipe_ctx->plane_res, \
Ddc_dmub_srv.c413 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
418 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
834 …>pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info()
836 …ipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info()
996 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; in dc_can_pipe_disable_cursor()
1012 r2 = test_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor()
1024 r2_half = split_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor()
1063 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dc_build_cursor_update_payload0()
1157 pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
1167 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
/openbsd/src/sys/dev/pci/drm/amd/display/amdgpu_dm/
Damdgpu_dm_trace.h386 const struct plane_resource *plane_res,
388 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
439 __entry->recout_x = plane_res->scl_data.recout.x;
440 __entry->recout_y = plane_res->scl_data.recout.y;
441 __entry->recout_w = plane_res->scl_data.recout.width;
442 __entry->recout_h = plane_res->scl_data.recout.height;
443 __entry->viewport_x = plane_res->scl_data.viewport.x;
444 __entry->viewport_y = plane_res->scl_data.viewport.y;
445 __entry->viewport_w = plane_res->scl_data.viewport.width;
446 __entry->viewport_h = plane_res->scl_data.viewport.height;
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c169 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
170 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dce/
Ddmub_psr.c341 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
343 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings()
344 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
Ddmub_replay.c152 if (pipe_ctx->plane_res.dpp) in dmub_replay_copy_settings()
153 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_replay_copy_settings()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/basics/
Ddce_calcs.c2825 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2827 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data()
2828 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2829 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2830 …data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.h… in populate_initial_data()
2831 …data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.v… in populate_initial_data()
2880 …data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.v… in populate_initial_data()
2881 …data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.vi… in populate_initial_data()
2884 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2885 …data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/inc/
Dcore_types.h425 struct plane_resource plane_res; member
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c117 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
Ddcn20_fpu.c1201 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = in dcn20_calculate_dlg_params()
1590 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; in dcn20_populate_dml_pipes_from_context()
1660 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
1665 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c120 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in rn_update_clocks_update_dpp_dto()