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Searched refs:plane_id (Results 1 – 25 of 26) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/i915/display/
Dintel_sprite_regs.h230 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument
231 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
232 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument
233 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
237 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) argument
266 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) argument
270 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) argument
274 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) argument
282 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) argument
290 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) argument
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Dskl_universal_plane.c248 enum plane_id plane_id) in icl_is_nv12_y_plane() argument
251 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); in icl_is_nv12_y_plane()
259 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) in icl_is_hdr_plane() argument
262 icl_hdr_plane_mask() & BIT(plane_id); in icl_is_hdr_plane()
602 enum plane_id plane_id = plane->id; in icl_program_input_csc() local
644 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), in icl_program_input_csc()
646 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), in icl_program_input_csc()
648 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), in icl_program_input_csc()
650 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), in icl_program_input_csc()
652 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), in icl_program_input_csc()
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Dskl_universal_plane.h19 enum plane_id;
23 enum pipe pipe, enum plane_id plane_id);
36 enum plane_id plane_id);
38 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
Dintel_dpt_common.c18 enum plane_id plane_id; in intel_dpt_configure() local
20 for_each_plane_id_on_crtc(crtc, plane_id) { in intel_dpt_configure()
21 if (plane_id == PLANE_CURSOR) in intel_dpt_configure()
24 intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id), in intel_dpt_configure()
Dskl_watermark.c351 enum plane_id plane_id; in skl_crtc_can_enable_sagv() local
363 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv()
365 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
385 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv()
387 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
403 enum plane_id plane_id; in tgl_crtc_can_enable_sagv() local
408 for_each_plane_id_on_crtc(crtc, plane_id) { in tgl_crtc_can_enable_sagv()
410 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
794 const enum plane_id plane_id, in skl_ddb_get_hw_plane_state() argument
801 if (plane_id == PLANE_CURSOR) { in skl_ddb_get_hw_plane_state()
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Dintel_sprite.c72 enum plane_id plane_id = plane->id; in chv_sprite_update_csc() local
103 intel_de_write_fw(display, SPCSCYGOFF(plane_id), in chv_sprite_update_csc()
105 intel_de_write_fw(display, SPCSCCBOFF(plane_id), in chv_sprite_update_csc()
107 intel_de_write_fw(display, SPCSCCROFF(plane_id), in chv_sprite_update_csc()
110 intel_de_write_fw(display, SPCSCC01(plane_id), in chv_sprite_update_csc()
112 intel_de_write_fw(display, SPCSCC23(plane_id), in chv_sprite_update_csc()
114 intel_de_write_fw(display, SPCSCC45(plane_id), in chv_sprite_update_csc()
116 intel_de_write_fw(display, SPCSCC67(plane_id), in chv_sprite_update_csc()
118 intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8])); in chv_sprite_update_csc()
120 intel_de_write_fw(display, SPCSCYGICLAMP(plane_id), in chv_sprite_update_csc()
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Di9xx_wm.c835 static int g4x_plane_fifo_size(enum plane_id plane_id, int level) in g4x_plane_fifo_size() argument
851 switch (plane_id) { in g4x_plane_fifo_size()
859 MISSING_CASE(plane_id); in g4x_plane_fifo_size()
934 int level, enum plane_id plane_id, u16 value) in g4x_raw_plane_wm_set() argument
942 dirty |= raw->plane[plane_id] != value; in g4x_raw_plane_wm_set()
943 raw->plane[plane_id] = value; in g4x_raw_plane_wm_set()
977 enum plane_id plane_id = plane->id; in g4x_raw_plane_wm_compute() local
982 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0); in g4x_raw_plane_wm_compute()
983 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute()
993 max_wm = g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_compute()
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Dskl_watermark.h52 enum plane_id plane_id,
55 enum plane_id plane_id);
Dintel_bw.c778 enum plane_id plane_id; in intel_bw_crtc_data_rate() local
780 for_each_plane_id_on_crtc(crtc, plane_id) { in intel_bw_crtc_data_rate()
785 if (plane_id == PLANE_CURSOR) in intel_bw_crtc_data_rate()
788 data_rate += crtc_state->data_rate[plane_id]; in intel_bw_crtc_data_rate()
791 data_rate += crtc_state->data_rate_y[plane_id]; in intel_bw_crtc_data_rate()
1168 enum plane_id plane_id, in skl_plane_calc_dbuf_bw() argument
1183 crtc_bw->active_planes[slice] |= BIT(plane_id); in skl_plane_calc_dbuf_bw()
1193 enum plane_id plane_id; in skl_crtc_calc_dbuf_bw() local
1200 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_calc_dbuf_bw()
1205 if (plane_id == PLANE_CURSOR) in skl_crtc_calc_dbuf_bw()
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Dintel_atomic_plane.c697 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) in intel_crtc_get_plane() argument
703 if (plane->id == plane_id) in intel_crtc_get_plane()
768 enum plane_id plane_id = plane->id; in skl_next_plane_to_commit() local
771 !(*update_mask & BIT(plane_id))) in skl_next_plane_to_commit()
774 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id], in skl_next_plane_to_commit()
775 ddb, I915_MAX_PLANES, plane_id) || in skl_next_plane_to_commit()
776 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
777 ddb_y, I915_MAX_PLANES, plane_id)) in skl_next_plane_to_commit()
780 *update_mask &= ~BIT(plane_id); in skl_next_plane_to_commit()
781 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id]; in skl_next_plane_to_commit()
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Dintel_frontbuffer.h63 #define INTEL_FRONTBUFFER(pipe, plane_id) \ argument
64 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe));
Dintel_fbc_regs.h66 #define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) argument
Dintel_cursor.c617 enum plane_id plane_id = plane->id; in skl_write_cursor_wm() local
621 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_cursor_wm()
626 skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); in skl_write_cursor_wm()
629 skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); in skl_write_cursor_wm()
632 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_write_cursor_wm()
Dintel_display_limits.h62 enum plane_id { enum
Dintel_atomic_plane.h19 enum plane_id;
Dintel_sprite_uapi.c67 plane = drm_plane_find(dev, file_priv, set->plane_id); in intel_sprite_set_colorkey_ioctl()
Dintel_display_debugfs.c688 enum plane_id plane_id; in i915_ddb_info() local
692 for_each_plane_id_on_crtc(crtc, plane_id) { in i915_ddb_info()
693 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; in i915_ddb_info()
694 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, in i915_ddb_info()
Dintel_display_types.h1548 enum plane_id id;
/openbsd/src/sys/dev/pci/drm/i915/gvt/
Ddmabuf.c257 int plane_id) in vgpu_get_plane_info() argument
265 if (plane_id == DRM_PLANE_TYPE_PRIMARY) { in vgpu_get_plane_info()
295 } else if (plane_id == DRM_PLANE_TYPE_CURSOR) { in vgpu_get_plane_info()
317 gvt_vgpu_err("invalid plane id:%d\n", plane_id); in vgpu_get_plane_info()
/openbsd/src/sys/dev/pci/drm/include/uapi/drm/
Ddrm_mode.h297 __u32 plane_id; member
334 __u32 plane_id; member
Di915_drm.h1926 __u32 plane_id; member
/openbsd/src/sys/dev/pci/drm/
Ddrm_plane.c836 plane = drm_plane_find(dev, file_priv, plane_resp->plane_id); in drm_mode_getplane()
856 plane_resp->plane_id = plane->base.id; in drm_mode_getplane()
1124 plane = drm_plane_find(dev, file_priv, plane_req->plane_id); in drm_mode_setplane()
1127 plane_req->plane_id); in drm_mode_setplane()
/openbsd/src/sys/dev/pci/drm/amd/display/amdgpu_dm/
Damdgpu_dm_trace.h228 __field(uint32_t, plane_id)
257 __entry->plane_id = state->plane->base.id;
292 __entry->plane_id, __entry->plane_type, __entry->plane_state,
Damdgpu_dm.c4785 struct amdgpu_mode_info *mode_info, int plane_id, in initialize_plane() argument
4806 possible_crtcs = 1 << plane_id; in initialize_plane()
4807 if (plane_id >= dm->dc->caps.max_streams) in initialize_plane()
4819 mode_info->planes[plane_id] = plane; in initialize_plane()
/openbsd/src/sys/dev/pci/drm/i915/
Di915_reg.h1745 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MA… argument
2244 #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1) argument
2267 #define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1) argument
2537 #define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ argument
2538 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */

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