1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include <linux/pm_qos.h>
36
37 #include <drm/ttm/ttm_device.h>
38
39 #include "vga.h"
40
41 struct inteldrm_softc;
42 #define drm_i915_private inteldrm_softc
43
44 #include "display/intel_display_limits.h"
45 #include "display/intel_display_core.h"
46
47 #include "gem/i915_gem_context_types.h"
48 #include "gem/i915_gem_shrinker.h"
49 #include "gem/i915_gem_stolen.h"
50
51 #include "gt/intel_engine.h"
52 #include "gt/intel_gt_types.h"
53 #include "gt/intel_region_lmem.h"
54 #include "gt/intel_workarounds.h"
55 #include "gt/uc/intel_uc.h"
56
57 #include "soc/intel_pch.h"
58
59 #include "i915_drm_client.h"
60 #include "i915_gem.h"
61 #include "i915_gpu_error.h"
62 #include "i915_params.h"
63 #include "i915_perf_types.h"
64 #include "i915_scheduler.h"
65 #include "i915_utils.h"
66 #include "intel_device_info.h"
67 #include "intel_memory_region.h"
68 #include "intel_runtime_pm.h"
69 #include "intel_step.h"
70 #include "intel_uncore.h"
71
72 #include "drm.h"
73
74 #include <dev/ic/mc6845reg.h>
75 #include <dev/ic/pcdisplayvar.h>
76 #include <dev/ic/vgareg.h>
77 #include <dev/ic/vgavar.h>
78
79 #include <sys/task.h>
80 #include <dev/pci/vga_pcivar.h>
81 #include <dev/wscons/wsconsio.h>
82 #include <dev/wscons/wsdisplayvar.h>
83 #include <dev/rasops/rasops.h>
84
85 struct drm_i915_clock_gating_funcs;
86 struct vlv_s0ix_state;
87 struct intel_pxp;
88
89 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
90
91 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */
92 struct i915_dsm {
93 /*
94 * The start and end of DSM which we can optionally use to create GEM
95 * objects backed by stolen memory.
96 *
97 * Note that usable_size tells us exactly how much of this we are
98 * actually allowed to use, given that some portion of it is in fact
99 * reserved for use by hardware functions.
100 */
101 struct resource stolen;
102
103 /*
104 * Reserved portion of DSM.
105 */
106 struct resource reserved;
107
108 /*
109 * Total size minus reserved ranges.
110 *
111 * DSM is segmented in hardware with different portions offlimits to
112 * certain functions.
113 *
114 * The drm_mm is initialised to the total accessible range, as found
115 * from the PCI config. On Broadwell+, this is further restricted to
116 * avoid the first page! The upper end of DSM is reserved for hardware
117 * functions and similarly removed from the accessible range.
118 */
119 resource_size_t usable_size;
120 };
121
122 struct i915_suspend_saved_registers {
123 u32 saveDSPARB;
124 u32 saveSWF0[16];
125 u32 saveSWF1[16];
126 u32 saveSWF3[3];
127 u16 saveGCDGMBUS;
128 };
129
130 #define MAX_L3_SLICES 2
131 struct intel_l3_parity {
132 u32 *remap_info[MAX_L3_SLICES];
133 struct work_struct error_work;
134 int which_slice;
135 };
136
137 struct i915_gem_mm {
138 /*
139 * Shortcut for the stolen region. This points to either
140 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
141 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
142 * support stolen.
143 */
144 struct intel_memory_region *stolen_region;
145 /** Memory allocator for GTT stolen memory */
146 struct drm_mm stolen;
147 /** Protects the usage of the GTT stolen memory allocator. This is
148 * always the inner lock when overlapping with struct_mutex. */
149 struct rwlock stolen_lock;
150
151 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
152 spinlock_t obj_lock;
153
154 /**
155 * List of objects which are purgeable.
156 */
157 struct list_head purge_list;
158
159 /**
160 * List of objects which have allocated pages and are shrinkable.
161 */
162 struct list_head shrink_list;
163
164 /**
165 * List of objects which are pending destruction.
166 */
167 struct llist_head free_list;
168 struct work_struct free_work;
169 /**
170 * Count of objects pending destructions. Used to skip needlessly
171 * waiting on an RCU barrier if no objects are waiting to be freed.
172 */
173 atomic_t free_count;
174
175 /**
176 * tmpfs instance used for shmem backed objects
177 */
178 struct vfsmount *gemfs;
179
180 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
181
182 struct notifier_block oom_notifier;
183 struct notifier_block vmap_notifier;
184 struct shrinker *shrinker;
185
186 /* shrinker accounting, also useful for userland debugging */
187 u64 shrink_memory;
188 u32 shrink_count;
189 };
190
191 struct i915_virtual_gpu {
192 struct rwlock lock; /* serialises sending of g2v_notify command pkts */
193 bool active;
194 u32 caps;
195 u32 *initial_mmio;
196 u8 *initial_cfg_space;
197 struct list_head entry;
198 };
199
200 struct i915_selftest_stash {
201 atomic_t counter;
202 struct ida mock_region_instances;
203 };
204
205
206 struct inteldrm_softc {
207 #ifdef __OpenBSD__
208 struct device sc_dev;
209 bus_dma_tag_t dmat;
210 bus_space_tag_t iot;
211 bus_space_tag_t bst;
212 bus_space_handle_t opregion_ioh;
213 bus_space_handle_t opregion_rvda_ioh;
214 bus_size_t opregion_rvda_size;
215 #endif
216
217 struct drm_device drm;
218
219 struct intel_display display;
220
221 /* FIXME: Device release actions should all be moved to drmm_ */
222 bool do_release;
223
224 /* i915 device parameters */
225 struct i915_params params;
226
227 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */
228 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
229 struct intel_driver_caps caps;
230
231 struct i915_dsm dsm;
232
233 #ifdef __OpenBSD__
234 struct pci_attach_args *pa;
235 pci_chipset_tag_t pc;
236 pcitag_t tag;
237 struct extent *memex;
238 pci_intr_handle_t ih;
239 irqreturn_t(*irq_handler) (int, void *);
240 void *irqh;
241
242 struct vga_pci_bar bar;
243 struct vga_pci_bar *vga_regs;
244
245 const struct pci_device_id *id;
246
247 int console;
248 int primary;
249 int nscreens;
250 void (*switchcb)(void *, int, int);
251 void *switchcbarg;
252 void *switchcookie;
253 struct task switchtask;
254 struct rasops_info ro;
255
256 struct task burner_task;
257 int burner_fblank;
258
259 struct backlight_device *backlight;
260
261 union flush {
262 struct {
263 bus_space_tag_t bst;
264 bus_space_handle_t bsh;
265 } i9xx;
266 struct {
267 bus_dma_segment_t seg;
268 caddr_t kva;
269 } i8xx;
270 } ifp;
271 struct vm_page *pgs;
272 #endif
273
274 struct intel_uncore uncore;
275 struct intel_uncore_mmio_debug mmio_debug;
276
277 struct i915_virtual_gpu vgpu;
278
279 struct intel_gvt *gvt;
280
281 struct {
282 struct pci_dev *pdev;
283 struct resource mch_res;
284 bool mchbar_need_disable;
285 } gmch;
286
287 /*
288 * Chaining user engines happens in multiple stages, starting with a
289 * simple lock-less linked list created by intel_engine_add_user(),
290 * which later gets sorted and converted to an intermediate regular
291 * list, just to be converted once again to its final rb tree structure
292 * in intel_engines_driver_register().
293 *
294 * Make sure to use the right iterator helper, depending on if the code
295 * in question runs before or after intel_engines_driver_register() --
296 * for_each_uabi_engine() can only be used afterwards!
297 */
298 union {
299 struct llist_head uabi_engines_llist;
300 struct list_head uabi_engines_list;
301 struct rb_root uabi_engines;
302 };
303 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
304
305 /* protects the irq masks */
306 spinlock_t irq_lock;
307
308 /* Sideband mailbox protection */
309 struct rwlock sb_lock;
310 struct pm_qos_request sb_qos;
311
312 /** Cached value of IMR to avoid reads in updating the bitfield */
313 u32 irq_mask;
314
315 bool preserve_bios_swizzle;
316
317 unsigned int fsb_freq, mem_freq, is_ddr3;
318
319 unsigned int hpll_freq;
320 unsigned int czclk_freq;
321
322 /**
323 * wq - Driver workqueue for GEM.
324 *
325 * NOTE: Work items scheduled here are not allowed to grab any modeset
326 * locks, for otherwise the flushing done in the pageflip code will
327 * result in deadlocks.
328 */
329 struct workqueue_struct *wq;
330
331 /**
332 * unordered_wq - internal workqueue for unordered work
333 *
334 * This workqueue should be used for all unordered work
335 * scheduling within i915, which used to be scheduled on the
336 * system_wq before moving to a driver instance due
337 * deprecation of flush_scheduled_work().
338 */
339 struct workqueue_struct *unordered_wq;
340
341 /* pm private clock gating functions */
342 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
343
344 /* PCH chipset type */
345 enum intel_pch pch_type;
346 unsigned short pch_id;
347
348 unsigned long gem_quirks;
349
350 struct i915_gem_mm mm;
351
352 struct intel_l3_parity l3_parity;
353
354 /*
355 * edram size in MB.
356 * Cannot be determined by PCIID. You must always read a register.
357 */
358 u32 edram_size_mb;
359
360 struct i915_gpu_error gpu_error;
361
362 u32 suspend_count;
363 struct i915_suspend_saved_registers regfile;
364 struct vlv_s0ix_state *vlv_s0ix_state;
365
366 struct dram_info {
367 bool wm_lv_0_adjust_needed;
368 u8 num_channels;
369 bool symmetric_memory;
370 enum intel_dram_type {
371 INTEL_DRAM_UNKNOWN,
372 INTEL_DRAM_DDR3,
373 INTEL_DRAM_DDR4,
374 INTEL_DRAM_LPDDR3,
375 INTEL_DRAM_LPDDR4,
376 INTEL_DRAM_DDR5,
377 INTEL_DRAM_LPDDR5,
378 INTEL_DRAM_GDDR,
379 } type;
380 u8 num_qgv_points;
381 u8 num_psf_gv_points;
382 } dram_info;
383
384 struct intel_runtime_pm runtime_pm;
385
386 struct i915_perf perf;
387
388 struct i915_hwmon *hwmon;
389
390 struct intel_gt *gt[I915_MAX_GT];
391
392 struct kobject *sysfs_gt;
393
394 /* Quick lookup of media GT (current platforms only have one) */
395 struct intel_gt *media_gt;
396
397 struct {
398 struct i915_gem_contexts {
399 spinlock_t lock; /* locks list */
400 struct list_head list;
401 } contexts;
402
403 /*
404 * We replace the local file with a global mappings as the
405 * backing storage for the mmap is on the device and not
406 * on the struct file, and we do not want to prolong the
407 * lifetime of the local fd. To minimise the number of
408 * anonymous inodes we create, we use a global singleton to
409 * share the global mapping.
410 */
411 struct file *mmap_singleton;
412 } gem;
413
414 struct intel_pxp *pxp;
415
416 bool irq_enabled;
417
418 struct i915_pmu pmu;
419
420 /* The TTM device structure. */
421 struct ttm_device bdev;
422
423 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
424
425 /*
426 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
427 * will be rejected. Instead look for a better place.
428 */
429 };
430
to_i915(const struct drm_device * dev)431 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
432 {
433 return container_of(dev, struct drm_i915_private, drm);
434 }
435
kdev_to_i915(struct device * kdev)436 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
437 {
438 struct drm_device *drm = dev_get_drvdata(kdev);
439
440 return drm ? to_i915(drm) : NULL;
441 }
442
pdev_to_i915(struct pci_dev * pdev)443 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
444 {
445 struct drm_device *drm = pci_get_drvdata(pdev);
446
447 return drm ? to_i915(drm) : NULL;
448 }
449
to_gt(const struct drm_i915_private * i915)450 static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
451 {
452 return i915->gt[0];
453 }
454
455 #define rb_to_uabi_engine(rb) \
456 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
457
458 #define for_each_uabi_engine(engine__, i915__) \
459 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
460 (engine__); \
461 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
462
463 #define INTEL_INFO(i915) ((i915)->__info)
464 #define RUNTIME_INFO(i915) (&(i915)->__runtime)
465 #define DRIVER_CAPS(i915) (&(i915)->caps)
466
467 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
468
469 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
470
471 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
472 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
473 RUNTIME_INFO(i915)->graphics.ip.rel)
474 #define IS_GRAPHICS_VER(i915, from, until) \
475 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
476
477 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
478 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
479 RUNTIME_INFO(i915)->media.ip.rel)
480 #define IS_MEDIA_VER(i915, from, until) \
481 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
482
483 #define INTEL_REVID(i915) ((i915)->drm.pdev->revision)
484
485 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
486 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
487
488 #define IS_GRAPHICS_STEP(__i915, since, until) \
489 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
490 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
491
492 #define IS_MEDIA_STEP(__i915, since, until) \
493 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
494 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
495
496 static __always_inline unsigned int
__platform_mask_index(const struct intel_runtime_info * info,enum intel_platform p)497 __platform_mask_index(const struct intel_runtime_info *info,
498 enum intel_platform p)
499 {
500 const unsigned int pbits =
501 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
502
503 /* Expand the platform_mask array if this fails. */
504 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
505 pbits * ARRAY_SIZE(info->platform_mask));
506
507 return p / pbits;
508 }
509
510 static __always_inline unsigned int
__platform_mask_bit(const struct intel_runtime_info * info,enum intel_platform p)511 __platform_mask_bit(const struct intel_runtime_info *info,
512 enum intel_platform p)
513 {
514 const unsigned int pbits =
515 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
516
517 return p % pbits + INTEL_SUBPLATFORM_BITS;
518 }
519
520 static inline u32
intel_subplatform(const struct intel_runtime_info * info,enum intel_platform p)521 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
522 {
523 const unsigned int pi = __platform_mask_index(info, p);
524
525 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
526 }
527
528 static __always_inline bool
IS_PLATFORM(const struct drm_i915_private * i915,enum intel_platform p)529 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
530 {
531 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
532 const unsigned int pi = __platform_mask_index(info, p);
533 const unsigned int pb = __platform_mask_bit(info, p);
534
535 #ifdef notyet
536 BUILD_BUG_ON(!__builtin_constant_p(p));
537 #endif
538
539 return info->platform_mask[pi] & BIT(pb);
540 }
541
542 static __always_inline bool
IS_SUBPLATFORM(const struct drm_i915_private * i915,enum intel_platform p,unsigned int s)543 IS_SUBPLATFORM(const struct drm_i915_private *i915,
544 enum intel_platform p, unsigned int s)
545 {
546 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
547 const unsigned int pi = __platform_mask_index(info, p);
548 const unsigned int pb = __platform_mask_bit(info, p);
549 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
550 const u32 mask = info->platform_mask[pi];
551
552 #ifdef notyet
553 BUILD_BUG_ON(!__builtin_constant_p(p));
554 BUILD_BUG_ON(!__builtin_constant_p(s));
555 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
556 #endif
557
558 /* Shift and test on the MSB position so sign flag can be used. */
559 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
560 }
561
562 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
563 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
564
565 #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
566 #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
567 #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
568 #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
569 #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
570 #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
571 #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
572 #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
573 #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
574 #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
575 #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
576 #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
577 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
578 #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
579 #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
580 #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
581 #define IS_IRONLAKE_M(i915) \
582 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
583 #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
584 #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
585 #define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
586 INTEL_INFO(i915)->gt == 1)
587 #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
588 #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
589 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
590 #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
591 #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
592 #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
593 #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
594 #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
595 #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
596 #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
597 #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
598 #define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
599 #define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
600 #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
601 #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
602 #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
603 #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
604 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
605 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
606 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
607 /*
608 * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE,
609 * so we need to define these even on platforms that the i915 base driver
610 * doesn't support. Ensure the parameter is used in the definition to
611 * avoid 'unused variable' warnings when compiling the shared display code
612 * for i915.
613 */
614 #define IS_LUNARLAKE(i915) (0 && i915)
615 #define IS_BATTLEMAGE(i915) (0 && i915)
616
617 #define IS_ARROWLAKE_H(i915) \
618 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H)
619 #define IS_ARROWLAKE_U(i915) \
620 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U)
621 #define IS_ARROWLAKE_S(i915) \
622 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S)
623 #define IS_DG2_G10(i915) \
624 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
625 #define IS_DG2_G11(i915) \
626 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
627 #define IS_DG2_G12(i915) \
628 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
629 #define IS_RAPTORLAKE_S(i915) \
630 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
631 #define IS_ALDERLAKE_P_N(i915) \
632 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
633 #define IS_RAPTORLAKE_P(i915) \
634 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
635 #define IS_RAPTORLAKE_U(i915) \
636 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
637 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
638 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
639 #define IS_BROADWELL_ULT(i915) \
640 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
641 #define IS_BROADWELL_ULX(i915) \
642 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
643 #define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
644 INTEL_INFO(i915)->gt == 3)
645 #define IS_HASWELL_ULT(i915) \
646 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
647 #define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \
648 INTEL_INFO(i915)->gt == 3)
649 #define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \
650 INTEL_INFO(i915)->gt == 1)
651 /* ULX machines are also considered ULT. */
652 #define IS_HASWELL_ULX(i915) \
653 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
654 #define IS_SKYLAKE_ULT(i915) \
655 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
656 #define IS_SKYLAKE_ULX(i915) \
657 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
658 #define IS_KABYLAKE_ULT(i915) \
659 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
660 #define IS_KABYLAKE_ULX(i915) \
661 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
662 #define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
663 INTEL_INFO(i915)->gt == 2)
664 #define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
665 INTEL_INFO(i915)->gt == 3)
666 #define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
667 INTEL_INFO(i915)->gt == 4)
668 #define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
669 INTEL_INFO(i915)->gt == 2)
670 #define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \
671 INTEL_INFO(i915)->gt == 3)
672 #define IS_COFFEELAKE_ULT(i915) \
673 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
674 #define IS_COFFEELAKE_ULX(i915) \
675 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
676 #define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \
677 INTEL_INFO(i915)->gt == 2)
678 #define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \
679 INTEL_INFO(i915)->gt == 3)
680
681 #define IS_COMETLAKE_ULT(i915) \
682 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
683 #define IS_COMETLAKE_ULX(i915) \
684 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
685 #define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
686 INTEL_INFO(i915)->gt == 2)
687
688 #define IS_ICL_WITH_PORT_F(i915) \
689 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
690
691 #define IS_TIGERLAKE_UY(i915) \
692 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
693
694 #define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
695 #define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
696 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
697
698 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
699 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
700
701 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
702 unsigned int first__ = (first); \
703 unsigned int count__ = (count); \
704 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
705 })
706
707 #define ENGINE_INSTANCES_MASK(gt, first, count) \
708 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
709
710 #define RCS_MASK(gt) \
711 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
712 #define BCS_MASK(gt) \
713 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
714 #define VDBOX_MASK(gt) \
715 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
716 #define VEBOX_MASK(gt) \
717 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
718 #define CCS_MASK(gt) \
719 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
720
721 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
722
723 /*
724 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
725 * All later gens can run the final buffer from the ppgtt
726 */
727 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
728
729 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
730 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
731 #define HAS_EDRAM(i915) ((i915)->edram_size_mb)
732 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
733 #define HAS_WT(i915) HAS_EDRAM(i915)
734
735 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
736
737 #define HAS_LOGICAL_RING_CONTEXTS(i915) \
738 (INTEL_INFO(i915)->has_logical_ring_contexts)
739 #define HAS_LOGICAL_RING_ELSQ(i915) \
740 (INTEL_INFO(i915)->has_logical_ring_elsq)
741
742 #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
743
744 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
745 #define HAS_PPGTT(i915) \
746 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
747 #define HAS_FULL_PPGTT(i915) \
748 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
749
750 #define HAS_PAGE_SIZES(i915, sizes) ({ \
751 GEM_BUG_ON((sizes) == 0); \
752 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
753 })
754
755 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
756 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
757
758 /* WaRsDisableCoarsePowerGating:skl,cnl */
759 #define NEEDS_WaRsDisableCoarsePowerGating(i915) \
760 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
761
762 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
763 * rows, which changed the alignment requirements and fence programming.
764 */
765 #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
766 !(IS_I915G(i915) || IS_I915GM(i915)))
767
768 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
769 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
770 #define HAS_RC6pp(i915) (false) /* HW was never validated */
771
772 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
773
774 #define HAS_HECI_PXP(i915) \
775 (INTEL_INFO(i915)->has_heci_pxp)
776
777 #define HAS_HECI_GSCFI(i915) \
778 (INTEL_INFO(i915)->has_heci_gscfi)
779
780 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
781
782 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
783 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
784
785 #define HAS_OA_BPC_REPORTING(i915) \
786 (INTEL_INFO(i915)->has_oa_bpc_reporting)
787 #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
788 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
789 #define HAS_OAM(i915) \
790 (INTEL_INFO(i915)->has_oam)
791
792 /*
793 * Set this flag, when platform requires 64K GTT page sizes or larger for
794 * device local memory access.
795 */
796 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
797
798 #define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id))
799 #define HAS_LMEM(i915) HAS_REGION(i915, INTEL_REGION_LMEM_0)
800
801 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
802
803 /*
804 * Platform has the dedicated compression control state for each lmem surfaces
805 * stored in lmem to support the 3D and media compression formats.
806 */
807 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
808
809 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
810
811 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
812
813 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
814
815 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
816
817 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
818
819 /* DPF == dynamic parity feature */
820 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
821 #define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
822 2 : HAS_L3_DPF(i915))
823
824 #define HAS_GUC_DEPRIVILEGE(i915) \
825 (INTEL_INFO(i915)->has_guc_deprivilege)
826
827 #define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
828
829 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
830
831 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
832
833 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
834 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
835
836 #endif
837