| /openbsd/src/gnu/usr.bin/binutils-2.17/cpu/ |
| D | m32c.cpu | 2810 (define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3)
2820 (encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8))
2821 (ifield-assertion (eq (.sym f- base -2) opc1))
5890 (define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
5892 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode))
5895 (define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem)
5896 (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
5899 (define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
5905 ; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) …
5908 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3))
[all …]
|
| /openbsd/src/gnu/usr.bin/binutils/opcodes/ |
| D | ia64-gen.c | 2602 opcodes_eq (opc1, opc2) in opcodes_eq() argument
2603 struct ia64_opcode *opc1; in opcodes_eq()
2609 if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type)
2610 || (opc1->num_outputs != opc2->num_outputs)
2611 || (opc1->flags != opc2->flags))
2615 if (opc1->operands[x] != opc2->operands[x])
2618 plen1 = get_prefix_len (opc1->name);
2621 if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0))
|
| /openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/ |
| D | ia64-gen.c | 2634 opcodes_eq (opc1, opc2) in opcodes_eq() argument
2635 struct ia64_opcode *opc1; in opcodes_eq()
2641 if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type)
2642 || (opc1->num_outputs != opc2->num_outputs)
2643 || (opc1->flags != opc2->flags))
2647 if (opc1->operands[x] != opc2->operands[x])
2650 plen1 = get_prefix_len (opc1->name);
2653 if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0))
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 4592 class SMLAL<bits<2> opc1, string asm>
4593 : AMulxyI64<0b0001010, opc1,
5373 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5375 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5376 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn,
5379 bits<4> opc1;
5392 let Inst{23-20} = opc1;
5397 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5399 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5400 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn,
[all …]
|
| D | ARMInstrThumb2.td | 4530 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4538 bits<3> opc1;
4545 let Inst{23-21} = opc1;
4555 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4563 bits<4> opc1;
4569 let Inst{7-4} = opc1;
4578 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4580 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
4583 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4584 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
[all …]
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
209 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
217 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
218 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
224 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
226 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
245 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
247 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
256 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
258 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 4621 class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
4628 let Inst{23-22} = opc1;
4661 class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
4663 : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> {
4673 multiclass MemTagStore<bits<2> opc1, string insn> {
4675 BaseMemTagStore<opc1, 0b10, insn, "\t$Rt, [$Rn, $offset]", "",
4678 BaseMemTagStore<opc1, 0b11, insn, "\t$Rt, [$Rn, $offset]!",
4683 BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset",
11056 bit opc1, bit opc2, RegisterOperand dst_reg,
11082 let Inst{15} = opc1;
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 6193 unsigned opc1 = fieldFromInstruction(Val, 4, 4); in DecoderForMRRC2AndMCRR2() local
6221 Inst.addOperand(MCOperand::createImm(opc1)); in DecoderForMRRC2AndMCRR2()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86InstrAVX512.td | 3168 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
3170 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode,
3173 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode,
|