| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoM.td | 71 def : PatGprGpr<mulhs, MULH>;
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| D | RISCVInstrInfoVSDPatterns.td | 722 defm : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH">;
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Support/ |
| D | KnownBits.h | 337 static KnownBits mulhs(const KnownBits &LHS, const KnownBits &RHS);
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Target/GlobalISel/ |
| D | SelectionDAGCompat.td | 63 def : GINodeEquiv<G_SMULH, mulhs>;
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| /openbsd/src/gnu/llvm/llvm/lib/Support/ |
| D | KnownBits.cpp | 513 KnownBits KnownBits::mulhs(const KnownBits &LHS, const KnownBits &RHS) { in mulhs() function in KnownBits
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 72 class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
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| D | Mips32r6InstrInfo.td | 593 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, II_MUH, mulhs>;
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| D | MicroMips32r6InstrInfo.td | 352 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 1493 def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>;
1563 def: Pat<(v2i32 (mulhs V2I32:$Rss, V2I32:$Rtt)),
1589 def: Pat<(v4i8 (mulhs V4I8:$Rs, V4I8:$Rt)),
1591 def: Pat<(v8i8 (mulhs V8I8:$Rss, V8I8:$Rtt)), (Mulhsb8 $Rss, $Rtt)>;
1606 def: Pat<(v2i16 (mulhs V2I16:$Rs, V2I16:$Rt)), (Mulhsh2 $Rs, $Rt)>;
1607 def: Pat<(v4i16 (mulhs V4I16:$Rss, V4I16:$Rtt)), (Mulhsh4 $Rss, $Rtt)>;
1767 def : Pat <(mulhs I64:$Rss, I64:$Rtt),
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| D | HexagonPatternsHVX.td | 916 def: Pat<(VecI8 (mulhs HVI8:$Vu, HVI8:$Vv)),
919 def: Pat<(VecI16 (mulhs HVI16:$Vu, HVI16:$Vv)),
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.td | 328 defm : MultiPat<mulhs, MPYM_rrr, MPYM_rru6, MPYM_rrlimm>;
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCInstrP10.td | 1695 [(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>;
1701 [(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>;
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| D | PPCInstr64Bit.td | 862 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
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| D | PPCInstrInfo.td | 2824 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | R600Instructions.td | 1136 inst, "MULHI_INT", mulhs> {
|
| D | VOP3Instructions.td | 158 defm V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", V_MUL_PROF<VOP_I32_I32_I32>, mulhs>;
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| D | SOPInstructions.td | 711 [(set i32:$sdst, (UniformBinFrag<mulhs> SSrc_b32:$src0, SSrc_b32:$src1))]>;
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 382 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2008 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
7590 def : Pat<(v16i8 (mulhs V128:$Rn, V128:$Rm)),
7595 def : Pat<(v8i16 (mulhs V128:$Rn, V128:$Rm)),
7600 def : Pat<(v4i32 (mulhs V128:$Rn, V128:$Rm)),
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3023 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
3042 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
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| D | ARMInstrInfo.td | 4456 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4473 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
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| D | ARMInstrMVE.td | 4799 defvar mulh = !if(VTI.Unsigned, mulhu, mulhs);
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 3232 Known = KnownBits::mulhs(Known, Known2); in computeKnownBits()
3254 Known = KnownBits::mulhs(Known, Known2); in computeKnownBits()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 727 defm MULTHS : I3<"mul.hi.s", mulhs>;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 3511 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
|