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Searched refs:mmUVD_SUVD_CGC_GATE (Results 1 – 14 of 14) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Duvd_v5_0.c638 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
676 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v5_0_enable_clock_gating()
733 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
764 WREG32(mmUVD_SUVD_CGC_GATE, data1);
Duvd_v6_0.c646 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
714 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1286 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1333 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v6_0_enable_clock_gating()
1391 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1424 WREG32(mmUVD_SUVD_CGC_GATE, data1);
Duvd_v7_0.c1619 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1666 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1675 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1708 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
Dvcn_v2_0.c598 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
623 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
680 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
Dvcn_v1_0.c576 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
601 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
737 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_5.c688 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
713 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
771 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
Dvcn_v3_0.c806 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
838 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); in vcn_v3_0_disable_clock_gating()
912 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/uvd/
Duvd_5_0_d.h89 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
Duvd_6_0_d.h105 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
Duvd_7_0_offset.h66 #define mmUVD_SUVD_CGC_GATE … macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h154 #define mmUVD_SUVD_CGC_GATE … macro
Dvcn_2_5_offset.h505 #define mmUVD_SUVD_CGC_GATE … macro
Dvcn_2_0_0_offset.h818 #define mmUVD_SUVD_CGC_GATE … macro
Dvcn_3_0_0_offset.h821 #define mmUVD_SUVD_CGC_GATE … macro