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Searched refs:mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 (Results 1 – 12 of 12) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h3747 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1758 macro
Ddce_10_0_d.h4374 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 macro
Ddce_11_0_d.h4329 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 macro
Ddce_11_2_d.h5561 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 macro
Ddce_12_0_offset.h1456 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h417 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … macro
Ddcn_3_0_1_offset.h612 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … macro
Ddcn_1_0_offset.h1042 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … macro
Ddcn_2_1_0_offset.h672 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … macro
Ddcn_3_0_2_offset.h584 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … macro
Ddcn_2_0_0_offset.h710 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … macro
Ddcn_3_0_0_offset.h600 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … macro