Searched refs:lvds (Results 1 – 9 of 9) sorted by relevance
1225 ATOM_LVDS_INFO_V12 *lvds; in get_embedded_panel_info_v1_2() local1233 lvds = in get_embedded_panel_info_v1_2()1236 if (!lvds) in get_embedded_panel_info_v1_2()1239 if (1 != lvds->sHeader.ucTableFormatRevision in get_embedded_panel_info_v1_2()1240 || 2 > lvds->sHeader.ucTableContentRevision) in get_embedded_panel_info_v1_2()1247 le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10; in get_embedded_panel_info_v1_2()1250 le16_to_cpu(lvds->sLCDTiming.usHActive); in get_embedded_panel_info_v1_2()1256 le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time); in get_embedded_panel_info_v1_2()1259 le16_to_cpu(lvds->sLCDTiming.usVActive); in get_embedded_panel_info_v1_2()1265 le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time); in get_embedded_panel_info_v1_2()[all …]
1435 struct lcd_info_v2_1 *lvds; in get_embedded_panel_info_v2_1() local1443 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); in get_embedded_panel_info_v2_1()1445 if (!lvds) in get_embedded_panel_info_v2_1()1449 if (!((lvds->table_header.format_revision == 2) in get_embedded_panel_info_v2_1()1450 && (lvds->table_header.content_revision >= 1))) in get_embedded_panel_info_v2_1()1456 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; in get_embedded_panel_info_v2_1()1458 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); in get_embedded_panel_info_v2_1()1464 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); in get_embedded_panel_info_v2_1()1466 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); in get_embedded_panel_info_v2_1()1472 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); in get_embedded_panel_info_v2_1()[all …]
1097 struct radeon_encoder_lvds *lvds; in radeon_legacy_get_lvds_info_from_regs() local1102 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); in radeon_legacy_get_lvds_info_from_regs()1104 if (!lvds) in radeon_legacy_get_lvds_info_from_regs()1111 lvds->panel_pwr_delay = 200; in radeon_legacy_get_lvds_info_from_regs()1112 lvds->panel_vcc_delay = 2000; in radeon_legacy_get_lvds_info_from_regs()1114 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_get_lvds_info_from_regs()1115 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; in radeon_legacy_get_lvds_info_from_regs()1116 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; in radeon_legacy_get_lvds_info_from_regs()1119 lvds->native_mode.vdisplay = in radeon_legacy_get_lvds_info_from_regs()1123 lvds->native_mode.vdisplay = in radeon_legacy_get_lvds_info_from_regs()[all …]
72 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_update() local73 panel_pwr_delay = lvds->panel_pwr_delay; in radeon_legacy_lvds_update()74 if (lvds->bl_dev) in radeon_legacy_lvds_update()75 backlight_level = lvds->backlight_level; in radeon_legacy_lvds_update()77 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_update() local78 panel_pwr_delay = lvds->panel_pwr_delay; in radeon_legacy_lvds_update()79 if (lvds->bl_dev) in radeon_legacy_lvds_update()80 backlight_level = lvds->backlight_level; in radeon_legacy_lvds_update()153 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; in radeon_legacy_lvds_dpms() local154 lvds->dpms_mode = mode; in radeon_legacy_lvds_dpms()[all …]
1631 struct radeon_encoder_atom_dig *lvds = NULL; in radeon_atombios_get_lvds_info() local1638 lvds = in radeon_atombios_get_lvds_info()1641 if (!lvds) in radeon_atombios_get_lvds_info()1644 lvds->native_mode.clock = in radeon_atombios_get_lvds_info()1646 lvds->native_mode.hdisplay = in radeon_atombios_get_lvds_info()1648 lvds->native_mode.vdisplay = in radeon_atombios_get_lvds_info()1650 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()1652 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in radeon_atombios_get_lvds_info()1654 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in radeon_atombios_get_lvds_info()1656 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in radeon_atombios_get_lvds_info()[all …]
799 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; in radeon_set_pll() local800 if (lvds) { in radeon_set_pll()801 if (lvds->use_bios_dividers) { in radeon_set_pll()802 pll_ref_div = lvds->panel_ref_divider; in radeon_set_pll()803 pll_fb_post_div = (lvds->panel_fb_divider | in radeon_set_pll()804 (lvds->panel_post_divider << 16)); in radeon_set_pll()
1975 struct amdgpu_encoder_atom_dig *lvds = NULL; in amdgpu_atombios_encoder_get_lcd_info() local1982 lvds = in amdgpu_atombios_encoder_get_lcd_info()1985 if (!lvds) in amdgpu_atombios_encoder_get_lcd_info()1988 lvds->native_mode.clock = in amdgpu_atombios_encoder_get_lcd_info()1990 lvds->native_mode.hdisplay = in amdgpu_atombios_encoder_get_lcd_info()1992 lvds->native_mode.vdisplay = in amdgpu_atombios_encoder_get_lcd_info()1994 lvds->native_mode.htotal = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()1996 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + in amdgpu_atombios_encoder_get_lcd_info()1998 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + in amdgpu_atombios_encoder_get_lcd_info()2000 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + in amdgpu_atombios_encoder_get_lcd_info()[all …]
847 u32 lvds; in intel_lvds_init() local868 lvds = intel_de_read(i915, lvds_reg); in intel_lvds_init()871 if ((lvds & LVDS_DETECTED) == 0) in intel_lvds_init()877 if ((lvds & LVDS_PORT_EN) == 0) { in intel_lvds_init()941 lvds_encoder->init_lvds_val = lvds; in intel_lvds_init()1002 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; in intel_lvds_init()
480 u32 lvds = intel_de_read(dev_priv, LVDS); in i9xx_crtc_clock_get() local485 if (lvds & LVDS_CLKB_POWER_UP) in i9xx_crtc_clock_get()