Searched refs:latencies (Results 1 – 25 of 40) sorted by relevance
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| /openbsd/src/sys/dev/pci/drm/i915/display/ |
| D | intel_wm.c | 216 const u16 *latencies; in pri_wm_latency_show() local
219 latencies = dev_priv->display.wm.skl_latency; in pri_wm_latency_show()
221 latencies = dev_priv->display.wm.pri_latency; in pri_wm_latency_show()
223 wm_latency_show(m, latencies); in pri_wm_latency_show()
231 const u16 *latencies; in spr_wm_latency_show() local
234 latencies = dev_priv->display.wm.skl_latency; in spr_wm_latency_show()
236 latencies = dev_priv->display.wm.spr_latency; in spr_wm_latency_show()
238 wm_latency_show(m, latencies); in spr_wm_latency_show()
246 const u16 *latencies; in cur_wm_latency_show() local
249 latencies = dev_priv->display.wm.skl_latency; in cur_wm_latency_show()
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| /openbsd/src/gnu/gcc/gcc/config/i386/ |
| D | ppro.md | 59 ;; - Include decoder latencies in the total reservation latencies.
68 ;; latencies of idiv and fdiv type insns.
124 ;; a latency already. Store latencies are not accounted for.
134 ;; they can only be decoded on decoder0. Modelling their latencies
205 ;; latencies due to branching. In particular, it has a fast way to
212 ;; the latencies for the compiler. Here I've made the choice to be
254 ;; These issue latencies are modelled via the ppro_div automaton.
298 ;; ??? where do these latencies come from? fadd has latency 3 and
400 ;; fdiv latencies depend on the mode of the operands. XFmode gives
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| D | k6.md | 117 ;; ??? Guessed latencies based on the old pipeline description.
263 ;; ??? Guessed latencies from the old pipeline description.
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| /openbsd/src/gnu/gcc/gcc/config/mips/ |
| D | 4k.md | 54 ;; unsigned divide - 8/16/24/32 bit operand have latencies 9/17/25/33
55 ;; signed divide - 8/16/24/32 bit operand have latencies 10/18/26/34
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| D | sr71k.md | 14 ;; published latencies. Emulation of out-of-order issue and the insn
171 ;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
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| D | 4130.md | 94 ;; & mfhi above. Note that the same latencies and repeat rates apply if we
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| D | sb1.md | 189 ;; Load latencies are 3 cycles for one load to another load or store (address
216 ;; ??? We cannot handle latencies properly for simple alu instructions
352 ;; Default for output dependencies is the difference in latencies, which is
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| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 814 // operations cannot be done at the same time and so their latencies are added.
826 // operations cannot be done at the same time and so their latencies are added.
836 // operations cannot be done at the same time and so their latencies are added.
847 // their latencies are added.
858 // operations cannot be done at the same time and so their latencies are added.
878 // Since the Load and the PM cannot be done at the same time the latencies are
1023 // latencies are not added together. Otherwise this is like having two
1035 // latencies are not added together. Otherwise this is like having two
1061 // latencies are not added together. Otherwise this is like having two
1072 // latencies are not added together. Otherwise this is like having two
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| D | PPCScheduleP9.td | 384 // 2 or 5 cycle latencies for the branch unit.
402 // so the latencies for their resources must be added.
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| /openbsd/src/gnu/usr.bin/gcc/gcc/config/i386/ |
| D | athlon.md | 111 ;; We use latencies 1 for definitions. This is OK to model colisions
112 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
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| /openbsd/src/gnu/usr.bin/gcc/gcc/config/mips/ |
| D | sr71k.md | 14 ;; published latencies. Emulation of out-of-order issue and the insn
183 ;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMScheduleM4.td | 35 // Some definitions of latencies we apply to different instructions
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| D | ARMScheduleM55.td | 47 // For this schedule, we currently model latencies and pipelines well for each
73 // one). These use normal resources and latencies, but set SingleIssue = 0.
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| D | ARMSchedule.td | 38 // shorter latencies to certain registers as needed in the example above.
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| D | ARMScheduleA9.td | 1975 // NEON has an odd mix of latencies. Simply name the write types by latency.
2310 // latencies here. WAW latencies are sometimes longer.
2369 // has a def operand so the WriteL latencies are unused.
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| /openbsd/src/gnu/gcc/gcc/config/arm/ |
| D | arm1136jfs.md | 255 ;; Call latencies are not predictable. A semi-arbitrary very large
304 ;; latencies are different depending on whether the address is 64-bit
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA53.td | 59 // shift-only instruction. These latencies will be incorrect when the
98 // accounted for in the WriteST* latencies below
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| D | AArch64SchedA55.td | 63 // These latencies are modeled without taking into account forwarding paths
64 // (the software optimisation guide lists latencies taking into account
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| D | AArch64SchedThunderX.td | 47 // latencies.
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| /openbsd/src/gnu/gcc/gcc/config/alpha/ |
| D | ev6.md | 32 ; all latencies by one, and adding bypasses within the cluster.
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| /openbsd/src/gnu/usr.bin/gcc/gcc/config/alpha/ |
| D | ev6.md | 32 ; all latencies by one, and adding bypasses within the cluster.
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| /openbsd/src/lib/libssl/test/ |
| D | times | 75 - The TCP round trip latencies, while slowing individual connections,
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| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | XRayExample.rst | 82 Functions with latencies: 29
155 Functions with latencies: 36652
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86Schedule.td | 732 // latencies. Since these latencies are not used for pipeline hazards,
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| /openbsd/src/gnu/llvm/llvm/docs/CommandGuide/ |
| D | llvm-mca.rst | 47 Scheduling models are not just used to compute instruction latencies and
962 Instruction latencies are computed by :program:`llvm-mca` with the help of the
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