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Searched refs:lane_count (Results 1 – 25 of 40) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/i915/display/
Dintel_dp_link_training.c406 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
409 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
429 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
434 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph()
502 crtc_state->lane_count, in intel_dp_get_adjust_train()
509 crtc_state->lane_count, in intel_dp_get_adjust_train()
543 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); in intel_dp_set_link_train()
544 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
614 crtc_state->lane_count, in intel_dp_set_signal_levels()
621 crtc_state->lane_count, in intel_dp_set_signal_levels()
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Dintel_dpio_phy.c315 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
324 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
339 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
598 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_dpio_phy_calc_lane_lat_optim_mask() argument
600 switch (lane_count) { in bxt_dpio_phy_calc_lane_lat_optim_mask()
608 MISSING_CASE(lane_count); in bxt_dpio_phy_calc_lane_lat_optim_mask()
737 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
750 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
758 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
766 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
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Dintel_dp.h58 int link_rate, int lane_count);
112 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
113 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
145 u32 link_clock, u32 lane_count,
162 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
164 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
Dvlv_dsi.c53 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
57 8 * 100), lane_count); in txbyteclkhs()
61 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
64 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1023 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1075 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1077 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1079 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1128 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1130 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
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Dintel_combo_phy.c261 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
268 switch (lane_count) { in intel_combo_phy_power_up_lanes()
279 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
286 switch (lane_count) { in intel_combo_phy_power_up_lanes()
296 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
Dvlv_dsi_pll.c48 int lane_count) in dsi_clk_from_pclk() argument
55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_pclk()
183 intel_dsi->lane_count); in vlv_dsi_pll_compute()
349 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_pclk()
488 intel_dsi->lane_count); in bxt_dsi_pll_compute()
Dintel_dp_mst.c106 overhead = drm_dp_bw_overhead(crtc_state->lane_count, in intel_dp_mst_bw_overhead()
129 intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, in intel_dp_mst_compute_m_n()
190 crtc_state->lane_count = limits->max_lane_count; in intel_dp_mst_find_vcpi_slots_for_bpp()
202 crtc_state->lane_count); in intel_dp_mst_find_vcpi_slots_for_bpp()
271 remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count); in intel_dp_mst_find_vcpi_slots_for_bpp()
678 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_dp_mst_compute_config()
1138 int link_rate, int lane_count) in intel_mst_probed_link_params_valid() argument
1141 intel_dp->link.mst_probed_lane_count == lane_count; in intel_mst_probed_link_params_valid()
1145 int link_rate, int lane_count) in intel_mst_set_probed_link_params() argument
1148 intel_dp->link.mst_probed_lane_count = lane_count; in intel_mst_set_probed_link_params()
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Dintel_dp.c380 int lane_count; in intel_dp_max_lane_count() local
383 lane_count = forced_lane_count(intel_dp); in intel_dp_max_lane_count()
385 lane_count = intel_dp->link.max_lane_count; in intel_dp_max_lane_count()
387 switch (lane_count) { in intel_dp_max_lane_count()
391 return lane_count; in intel_dp_max_lane_count()
393 MISSING_CASE(lane_count); in intel_dp_max_lane_count()
719 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) in intel_dp_link_config_get() argument
730 *lane_count = intel_dp_link_config_lane_count(lc); in intel_dp_link_config_get()
733 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) in intel_dp_link_config_index() argument
737 int lane_count_exp = ilog2(lane_count); in intel_dp_link_config_index()
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Dintel_dpio_phy.h40 u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
100 static inline u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_dpio_phy_calc_lane_lat_optim_mask() argument
Dintel_crtc_state_dump.c34 const char *id, unsigned int lane_count, in intel_dump_m_n_config() argument
38 id, lane_count, in intel_dump_m_n_config()
243 pipe_config->lane_count, in intel_crtc_state_dump()
246 pipe_config->lane_count, in intel_crtc_state_dump()
Dintel_combo_phy.h20 int lane_count, bool lane_reversal);
Dintel_ddi.c338 DDI_PORT_WIDTH(crtc_state->lane_count) | in intel_ddi_init_dp_buf_reg()
552 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
561 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
573 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
1111 if (crtc_state->lane_count == 4) in icl_combo_phy_loadgen_select()
2119 width = crtc_state->lane_count; in icl_program_mg_dp_mode()
2347 crtc_state->lane_count, in intel_ddi_power_up_lanes()
2428 static u8 mtl_get_port_width(u8 lane_count) in mtl_get_port_width() argument
2430 switch (lane_count) { in mtl_get_port_width()
2440 MISSING_CASE(lane_count); in mtl_get_port_width()
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Dintel_dp_link_training.h22 int link_bw, int rate_select, int lane_count,
Dintel_dsi.h67 unsigned int lane_count; member
Dintel_dsi.c39 return intel_dsi->pclk * bpp / intel_dsi->lane_count; in intel_dsi_bitrate()
Dintel_dp_tunnel.c61 int lane_count = intel_dp_max_common_lane_count(intel_dp); in get_current_link_bw() local
64 bw = intel_dp_max_link_data_rate(intel_dp, rate, lane_count); in get_current_link_bw()
65 *below_dprx_bw = bw < drm_dp_max_dprx_data_rate(rate, lane_count); in get_current_link_bw()
Dg4x_dp.c101 pipe_config->lane_count); in intel_dp_prepare()
126 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); in intel_dp_prepare()
395 pipe_config->lane_count = in intel_dp_get_config()
710 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); in intel_enable_dp()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dce/
Ddce_audio.c305 enum dc_lane_count lane_count, in get_av_stream_map_lane_count() argument
312 av_stream_map_lane_count = lane_count; in get_av_stream_map_lane_count()
326 enum dc_lane_count lane_count, in get_audio_sdp_overhead() argument
335 audio_sdp_overhead = lane_count * 2 + 8; in get_audio_sdp_overhead()
454 available_hblank_bw *= dp_link_info->lane_count; in calculate_available_hblank_bw_in_symbols()
487 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); in check_audio_bandwidth_dp()
489 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst); in check_audio_bandwidth_dp()
Ddce_link_encoder.c604 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
618 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in dce60_configure_encoder()
1138 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_output()
1177 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_mst_output()
1217 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_output()
1256 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_mst_output()
1338 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_dp_set_lane_settings()
1343 for (lane = 0; lane < link_settings->lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
/openbsd/src/sys/dev/pci/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c209 link->cur_link_settings.lane_count, in dp_link_settings_read()
216 link->verified_link_cap.lane_count, in dp_link_settings_read()
223 link->reported_link_cap.lane_count, in dp_link_settings_read()
230 link->preferred_link_setting.lane_count, in dp_link_settings_read()
330 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
464 prefer_link_settings.lane_count = param[0]; in dp_mst_link_setting()
659 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
660 link->preferred_link_setting.lane_count; in dp_phy_settings_write()
666 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
667 link->cur_link_settings.lane_count; in dp_phy_settings_write()
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/openbsd/src/sys/dev/pci/drm/amd/display/include/
Daudio_types.h42 enum dc_lane_count lane_count; member
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c155 cfg->link_settings.lane_count = in dce110_fill_display_configs()
156 stream->link->cur_link_settings.lane_count; in dce110_fill_display_configs()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/inc/hw/
Dlink_encoder.h219 uint32_t lane_count; member
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Damdgpu_atombios_dp.c204 int lane_count, in amdgpu_atombios_dp_get_adjust_train() argument
211 for (lane = 0; lane < lane_count; lane++) { in amdgpu_atombios_dp_get_adjust_train()
/openbsd/src/sys/dev/pci/drm/radeon/
Datombios_dp.c253 int lane_count, in dp_get_adjust_train() argument
260 for (lane = 0; lane < lane_count; lane++) { in dp_get_adjust_train()

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