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/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Damdgpu_jpeg.c41 INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler); in amdgpu_jpeg_sw_init()
42 rw_init(&adev->jpeg.jpeg_pg_lock, "jpgpg"); in amdgpu_jpeg_sw_init()
43 atomic_set(&adev->jpeg.total_submission_cnt, 0); in amdgpu_jpeg_sw_init()
47 adev->jpeg.indirect_sram = true; in amdgpu_jpeg_sw_init()
49 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in amdgpu_jpeg_sw_init()
50 if (adev->jpeg.harvest_config & (1 << i)) in amdgpu_jpeg_sw_init()
53 if (adev->jpeg.indirect_sram) { in amdgpu_jpeg_sw_init()
57 &adev->jpeg.inst[i].dpg_sram_bo, in amdgpu_jpeg_sw_init()
58 &adev->jpeg.inst[i].dpg_sram_gpu_addr, in amdgpu_jpeg_sw_init()
59 &adev->jpeg.inst[i].dpg_sram_cpu_addr); in amdgpu_jpeg_sw_init()
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Djpeg_v2_5.c63 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_5_early_init()
64 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; in jpeg_v2_5_early_init()
65 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in jpeg_v2_5_early_init()
68 adev->jpeg.harvest_config |= 1 << i; in jpeg_v2_5_early_init()
70 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | in jpeg_v2_5_early_init()
94 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_sw_init()
95 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()
100 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); in jpeg_v2_5_sw_init()
106 VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); in jpeg_v2_5_sw_init()
112 VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); in jpeg_v2_5_sw_init()
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Djpeg_v4_0_5.c74 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_5_early_init()
77 adev->jpeg.num_jpeg_inst = 2; in jpeg_v4_0_5_early_init()
86 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_5_early_init()
107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_sw_init()
108 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_sw_init()
113 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
119 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
125 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v4_0_5_sw_init()
138 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_5_sw_init()
139 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v4_0_5_sw_init()
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Djpeg_v4_0_3.c79 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; in jpeg_v4_0_3_early_init()
101 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
104 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); in jpeg_v4_0_3_sw_init()
117 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_sw_init()
120 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
121 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v4_0_3_sw_init()
123 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); in jpeg_v4_0_3_sw_init()
138 snprintf(ring->name, sizeof(ring->name), "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); in jpeg_v4_0_3_sw_init()
139 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_3_sw_init()
144 adev->jpeg.internal.jpeg_pitch[j] = in jpeg_v4_0_3_sw_init()
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Djpeg_v4_0.c60 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_early_init()
61 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_early_init()
85 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v4_0_sw_init()
91 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_sw_init()
97 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); in jpeg_v4_0_sw_init()
109 ring = adev->jpeg.inst->ring_dec; in jpeg_v4_0_sw_init()
115 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_sw_init()
120 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v4_0_sw_init()
121 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v4_0_sw_init()
160 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v4_0_hw_init()
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Djpeg_v5_0_0.c53 adev->jpeg.num_jpeg_inst = 1; in jpeg_v5_0_0_early_init()
54 adev->jpeg.num_jpeg_rings = 1; in jpeg_v5_0_0_early_init()
77 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v5_0_0_sw_init()
89 ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_sw_init()
95 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v5_0_0_sw_init()
100 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v5_0_0_sw_init()
101 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v5_0_0_sw_init()
136 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_hw_init()
166 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v5_0_0_hw_fini()
318 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v5_0_0_start_dpg_mode()
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Djpeg_v3_0.c66 adev->jpeg.num_jpeg_inst = 1; in jpeg_v3_0_early_init()
67 adev->jpeg.num_jpeg_rings = 1; in jpeg_v3_0_early_init()
90 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v3_0_sw_init()
102 ring = adev->jpeg.inst->ring_dec; in jpeg_v3_0_sw_init()
107 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v3_0_sw_init()
112 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v3_0_sw_init()
113 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v3_0_sw_init()
148 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v3_0_hw_init()
169 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v3_0_hw_fini()
327 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v3_0_start()
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Djpeg_v2_0.c52 adev->jpeg.num_jpeg_inst = 1; in jpeg_v2_0_early_init()
53 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_0_early_init()
76 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v2_0_sw_init()
88 ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_sw_init()
93 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v2_0_sw_init()
98 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v2_0_sw_init()
99 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); in jpeg_v2_0_sw_init()
134 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_hw_init()
155 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v2_0_hw_fini()
312 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_start()
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Djpeg_v1_0.c447 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v1_0_process_interrupt()
469 adev->jpeg.num_jpeg_inst = 1; in jpeg_v1_0_early_init()
470 adev->jpeg.num_jpeg_rings = 1; in jpeg_v1_0_early_init()
491 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->jpeg.inst->irq); in jpeg_v1_0_sw_init()
495 ring = adev->jpeg.inst->ring_dec; in jpeg_v1_0_sw_init()
498 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v1_0_sw_init()
503 adev->jpeg.internal.jpeg_pitch[0] = adev->jpeg.inst->external.jpeg_pitch[0] = in jpeg_v1_0_sw_init()
520 amdgpu_ring_fini(adev->jpeg.inst->ring_dec); in jpeg_v1_0_sw_fini()
533 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v1_0_start()
591 adev->jpeg.inst->ring_dec->funcs = &jpeg_v1_0_decode_ring_vm_funcs; in jpeg_v1_0_set_dec_ring_funcs()
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Damdgpu_jpeg.h47 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
49 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
90 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
91 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value; \
Dvcn_v1_0.c268 ring = adev->jpeg.inst->ring_dec; in vcn_v1_0_hw_init()
1270 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1271 new_state->fw_based, new_state->jpeg); in vcn_v1_0_pause_dpg_mode()
1323 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { in vcn_v1_0_pause_dpg_mode()
1326 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1327 new_state->fw_based, new_state->jpeg); in vcn_v1_0_pause_dpg_mode()
1332 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { in vcn_v1_0_pause_dpg_mode()
1354 ring = adev->jpeg.inst->ring_dec; in vcn_v1_0_pause_dpg_mode()
1380 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; in vcn_v1_0_pause_dpg_mode()
1852 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec)) in vcn_v1_0_idle_work_handler()
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Damdgpu_kms.c473 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in amdgpu_hw_ip_info()
474 if (adev->jpeg.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
477 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) in amdgpu_hw_ip_info()
478 if (adev->jpeg.inst[i].ring_dec[j].sched.ready) in amdgpu_hw_ip_info()
641 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; in amdgpu_info_ioctl()
665 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; in amdgpu_info_ioctl()
Daqua_vanjaram.c707 adev->jpeg.harvest_config = 0; in aqua_vanjaram_init_soc_config()
708 adev->jpeg.num_inst_per_aid = 1; in aqua_vanjaram_init_soc_config()
709 adev->jpeg.num_jpeg_inst = hweight32(adev->jpeg.inst_mask); in aqua_vanjaram_init_soc_config()
Damdgpu_discovery.c644 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
650 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
699 adev->jpeg.harvest_config |= in amdgpu_discovery_read_from_harvest_table()
704 adev->jpeg.inst_mask &= in amdgpu_discovery_read_from_harvest_table()
1313 adev->jpeg.inst_mask = 0; in amdgpu_discovery_reg_base_init()
1365 adev->jpeg.inst_mask |= in amdgpu_discovery_reg_base_init()
Damdgpu_vcn.h257 enum internal_dpg_state jpeg; member
Damdgpu.h1046 struct amdgpu_jpeg jpeg; member
/openbsd/src/share/misc/
Dmime.types70 image/jpeg jpeg jpg
/openbsd/src/usr.bin/file/magdir/
Djpeg1 # $OpenBSD: jpeg,v 1.5 2022/12/26 19:16:01 jmc Exp $
13 !:mime image/jpeg
/openbsd/src/gnu/usr.sbin/mkhybrid/src/
Dmore.mapping101 .jpe Raw 'JVWR' 'JPEG' "JPEGView - JPEG Picture (image/jpeg)"
102 .jpeg Raw 'JVWR' 'JPEG' "JPEGView - JPEG Picture (image/jpeg)"
103 .jpg Raw 'JVWR' 'JPEG' "JPEGView - JPEG Picture (image/jpeg)"
/openbsd/src/gnu/usr.bin/cvs/windows-NT/SCC/
DSCC.dsp105 # PROP Default_Filter "ico;cur;bmp;dlg;rc2;rct;bin;cnt;rtf;gif;jpg;jpeg;jpe"
/openbsd/src/sys/dev/pci/drm/amd/pm/swsmu/
Damdgpu_smu.c2054 adev->jpeg.cur_state = AMD_PG_STATE_GATE; in smu_hw_fini()
/openbsd/src/gnu/usr.bin/binutils/etc/
Dstandards.texi774 ``displaying jpeg images while in console mode'').
/openbsd/src/gnu/usr.bin/binutils-2.17/etc/
Dstandards.texi774 ``displaying jpeg images while in console mode'').