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Searched refs:isDivergent (Results 1 – 25 of 28) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Analysis/
DDivergenceAnalysis.cpp172 if (isDivergent(I)) in analyzeTemporalDivergence()
278 if (isDivergent(Phi)) in taintAndPushPhiNodes()
316 assert(isDivergent(*DivVal) && "Worklist invariant violated!"); in compute()
327 assert(isDivergent(I) && "Worklist invariant violated!"); in compute()
336 bool DivergenceAnalysisImpl::isDivergent(const Value &V) const { in isDivergent() function in DivergenceAnalysisImpl
343 return isDivergent(V) || isTemporalDivergent(*I.getParent(), V); in isDivergentUse()
397 OS << (DI.isDivergent(Arg) ? "DIVERGENT: " : " "); in run()
403 OS << (DI.isDivergent(I) ? "DIVERGENT: " : " "); in run()
DLegacyDivergenceAnalysis.cpp332 bool LegacyDivergenceAnalysisImpl::isDivergent(const Value *V) const { in isDivergent() function in LegacyDivergenceAnalysisImpl
334 return gpuDA->isDivergent(*V); in isDivergent()
370 OS << (isDivergent(&Arg) ? "DIVERGENT: " : " "); in print()
377 OS << (isDivergent(&I) ? "DIVERGENT: " : " "); in print()
DUniformityAnalysis.cpp24 return isDivergent((const Value *)&I); in hasDivergentDefs()
/openbsd/src/gnu/llvm/llvm/include/llvm/Analysis/
DDivergenceAnalysis.h78 bool isDivergent(const Value &Val) const;
167 bool isDivergent(const Value &V) const { in isDivergent() function
168 return ContainsIrreducible || DA->isDivergent(V); in isDivergent()
177 bool isUniform(const Value &V) const { return !isDivergent(V); } in isUniform()
DLegacyDivergenceAnalysis.h37 bool isDivergent(const Value *V) const;
43 bool isUniform(const Value *V) const { return !isDivergent(V); } in isUniform()
/openbsd/src/gnu/llvm/llvm/include/llvm/ADT/
DGenericUniformityInfo.h63 bool isDivergent(ConstValueRefT V) const;
66 bool isUniform(ConstValueRefT V) const { return !isDivergent(V); } in isUniform()
DGenericUniformityImpl.h377 bool isDivergent(const InstructionT &I) const { in isDivergent() function
385 bool isDivergent(ConstValueRefT V) const { return DivergentValues.count(V); } in isDivergent() function
809 if (isDivergent(I)) in analyzeTemporalDivergence()
1144 assert(isDivergent(DivVal) && "Worklist invariant violated!"); in compute()
1162 assert(isDivergent(*I) && "Worklist invariant violated!"); in compute()
1226 if (isDivergent(value)) in print()
1256 bool GenericUniformityInfo<ContextT>::isDivergent(ConstValueRefT V) const { in isDivergent() function
1257 return DA->isDivergent(V); in isDivergent()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPURewriteUndefForPHI.cpp108 if (DA->isDivergent(&PHI)) in INITIALIZE_PASS_DEPENDENCY()
150 !DA->isDivergent(DominateBB->getTerminator())) in INITIALIZE_PASS_DEPENDENCY()
DAMDGPUISelDAGToDAG.cpp849 unsigned Opc = OpcMap[0][N->isDivergent()][IsAdd]; in SelectADD_SUB_I64()
850 unsigned CarryOpc = OpcMap[1][N->isDivergent()][IsAdd]; in SelectADD_SUB_I64()
892 if (N->isDivergent()) { in SelectAddcSubb()
911 bool IsVALU = N->isDivergent(); in SelectUADDO_USUBO()
1270 if (N2->isDivergent()) { in SelectMUBUF()
1271 if (N3->isDivergent()) { in SelectMUBUF()
1287 } else if (N0->isDivergent()) { in SelectMUBUF()
1662 } else if (!LHS->isDivergent()) { in SelectGlobalSAddr()
1701 if (!LHS->isDivergent()) { in SelectGlobalSAddr()
1709 if (!SAddr && !RHS->isDivergent()) { in SelectGlobalSAddr()
[all …]
DSIISelLowering.cpp3010 if (Callee->isDivergent()) in isEligibleForTailCallOptimization()
5328 … Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent())); in LowerRETURNADDR()
5415 if (Op->isDivergent()) { in lowerXMUL_LOHI()
6745 if (!Offset->isDivergent()) { in lowerSBuffer()
8390 if (Addr->isDivergent() && Addr.getOpcode() == ISD::ADD) { in LowerINTRINSIC_VOID()
8394 if (LHS->isDivergent()) in LowerINTRINSIC_VOID()
8397 if (!LHS->isDivergent() && RHS.getOpcode() == ISD::ZERO_EXTEND && in LowerINTRINSIC_VOID()
8406 if (!Addr->isDivergent()) { in LowerINTRINSIC_VOID()
8621 if (Ld->getAlign() < Align(4) || Ld->isDivergent()) in widenLoad()
8759 if (!Op->isDivergent() && Alignment >= Align(4) && NumElements < 32) { in LowerLOAD()
[all …]
DSOPInstructions.td164 [{ return !N->isDivergent(); }]> {
176 [{ return !N->isDivergent(); }]> {
188 [{ return !N->isDivergent(); }]> {
200 [{ return N->isDivergent(); }]> {
535 [{ return !N->isDivergent(); }]
DSIISelLowering.h499 bool isDivergent) const override;
DVOP3Instructions.td424 if (!N->isDivergent())
429 // Note: Use !isDivergent as a conservative proxy for whether the value
433 if (!Operands[i]->isDivergent() &&
DVOPInstructions.td1022 [{ return N->isDivergent(); }]
1042 [{ return N->isDivergent(); }]> {
DAMDGPUISelLowering.cpp3430 if (!N->isDivergent()) in performMulCombine()
3533 if (Subtarget->hasSMulHi() && !N->isDivergent()) in performMulhsCombine()
3566 if (Subtarget->hasSMulHi() && !N->isDivergent()) in performMulhuCombine()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp367 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { in CreateReg() argument
368 return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent)); in CreateReg()
378 Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) { in CreateRegs() argument
389 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
397 return CreateRegs(V->getType(), DA && DA->isDivergent(V) && in CreateRegs()
DInstrEmitter.cpp107 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
214 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC)))); in CreateVirtualRegisters()
276 Op.getSimpleValueType(), Op.getNode()->isDivergent()); in getVR()
393 Op.getNode()->isDivergent() || in AddOperand()
450 MVT VT, bool isDivergent, const DebugLoc &DL) { in ConstrainForSubReg() argument
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
500 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
535 Node->isDivergent(), Node->getDebugLoc()); in EmitSubregNode()
571 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
DInstrEmitter.h86 bool isDivergent, const DebugLoc &DL);
DSelectionDAGDumper.cpp843 OS << " # D:" << isDivergent(); in print_details()
1068 if (isDivergent() && !VerboseDAGDumping) in print()
DSelectionDAG.cpp10371 if (To->isDivergent() != From->isDivergent()) in ReplaceAllUsesWith()
10429 if (To->isDivergent() != From->isDivergent()) in ReplaceAllUsesWith()
10479 To_IsDivergent |= ToOp->isDivergent(); in ReplaceAllUsesWith()
10482 if (To_IsDivergent != From->isDivergent()) in ReplaceAllUsesWith()
10543 if (To->isDivergent() != From->isDivergent()) in ReplaceAllUsesOfValueWith()
10604 if (Op.Val.getValueType() != MVT::Other && Op.getNode()->isDivergent()) in calculateDivergence()
10646 assert(calculateDivergence(N) == N->isDivergent() && in VerifyDAGDivergence()
12091 IsDivergent |= Ops[I].getNode()->isDivergent(); in createOperands()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DFunctionLoweringInfo.h202 Register CreateReg(MVT VT, bool isDivergent = false);
206 Register CreateRegs(Type *Ty, bool isDivergent = false);
DTargetLowering.h885 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
886 (void)isDivergent;
DSelectionDAGNodes.h712 bool isDivergent() const { return SDNodeBits.IsDivergent; }
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DMachineUniformityAnalysis.cpp26 if (isDivergent(op.getReg())) in hasDivergentDefs()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMISelLowering.h574 getRegClassFor(MVT VT, bool isDivergent = false) const override;

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