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Searched refs:isAssignedRegDep (Results 1 – 12 of 12) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonHazardRecognizer.cpp149 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
164 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
DHexagonSubtarget.cpp560 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in restoreLatency()
608 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in changeLatency()
624 if (I.isAssignedRegDep() && I.getLatency() == 0 && in getZeroLatency()
DHexagonVLIWPacketizer.cpp1922 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) || in calcStall()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGVLIW.cpp136 assert(!Succ.isAssignedRegDep() && in releaseSuccessors()
DScheduleDAGFast.cpp160 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()
189 if (Succ.isAssignedRegDep()) { in ScheduleNodeBottomUp()
484 if (Pred.isAssignedRegDep()) { in DelayForLiveRegsBottomUp()
DScheduleDAGRRList.cpp561 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()
775 if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) { in ScheduleNodeBottomUp()
844 if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){ in UnscheduleNodeBottomUp()
890 if (Succ.isAssignedRegDep()) { in UnscheduleNodeBottomUp()
904 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg && in UnscheduleNodeBottomUp()
1364 if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU) in DelayForLiveRegsBottomUp()
2877 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()
3053 assert(!Edge.isAssignedRegDep()); in PrescheduleNodesWithMultipleUses()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DScheduleDAG.cpp86 if (TRI && isAssignedRegDep()) in dump()
709 if (PredDep.isAssignedRegDep() && in WillCreateCycle()
DVLIWMachineScheduler.cpp711 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() && in SchedulingCost()
720 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() && in SchedulingCost()
DMachinePipeliner.cpp2745 if (SI.isAssignedRegDep() && !SI.getSUnit()->isBoundaryNode()) in isValidSchedule()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DScheduleDAG.h211 bool isAssignedRegDep() const { in isAssignedRegDep() function
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DGCNSchedStrategy.cpp965 if (D.isAssignedRegDep()) { in computeSUnitReadyCycle()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp6892 } else if (S.isAssignedRegDep()) { in tooMuchRegisterPressure()
6972 if (S.isAssignedRegDep()) { in tooMuchRegisterPressure()