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Searched refs:hasSubClassEq (Results 1 – 25 of 38) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86RegisterBankInfo.cpp46 if (X86::GR8RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
47 X86::GR16RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
48 X86::GR32RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
49 X86::GR64RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
50 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
51 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC)) in getRegBankFromRegClass()
54 if (X86::FR32XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
55 X86::FR64XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
56 X86::VR128XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
57 X86::VR256XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
[all …]
DX86DomainReassignment.cpp46 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
49 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
54 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
70 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
72 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
74 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
76 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
DX86InstrInfo.cpp3377 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
3378 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
3379 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
3608 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); in getLoadStoreRegOpcode()
3612 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3616 if (X86::VK16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3618 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
3621 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3623 if (X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3631 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp254 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
256 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
258 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in storeRegToStack()
260 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
262 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in storeRegToStack()
264 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
266 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
268 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
270 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
283 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
[all …]
DMips16InstrInfo.cpp116 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
135 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVInstrInfo.cpp478 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
482 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
485 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
488 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
491 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
493 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
495 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
497 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
499 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
501 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp545 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); in canFoldIntoCSel()
629 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
630 AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in canInsertSelect()
643 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
644 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
1208 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) && in UpdateOperandRegClass()
3841 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
3845 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
3847 else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
3854 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
[all …]
DAArch64MIPeepholeOpt.cpp284 !AArch64::GPR64allRegClass.hasSubClassEq(RC)) in visitINSERT()
/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp1554 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1555 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1556 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1557 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1585 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
1586 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
1588 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1589 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
1869 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1870 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
[all …]
DPPCVSXCopy.cpp54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
DPPCVSXSwapRemoval.cpp162 return RC->hasSubClassEq(MRI->getRegClass(Reg)); in isRegInClass()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DRegisterBank.cpp48 if (!RC.hasSubClassEq(&SubRC)) in verify()
DMachineCombiner.cpp188 return SrcRC->hasSuperClassEq(DstRC) || SrcRC->hasSubClassEq(DstRC); in isTransientMI()
/openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp524 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
527 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
563 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
566 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h125 return RC != this && hasSubClassEq(RC); in hasSubClass()
129 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
142 return RC->hasSubClassEq(this); in hasSuperClassEq()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARC/
DARCInstrInfo.cpp309 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
337 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp178 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
188 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
222 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
231 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
DARMBaseInstrInfo.cpp1131 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1142 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1149 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1156 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1167 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1174 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1195 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in storeRegToStackSlot()
1211 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
1223 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1247 if (ARM::QQPRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
[all …]
DThumbRegisterInfo.cpp48 if (ARM::tGPRRegClass.hasSubClassEq(RC)) in getLargestLegalSuperClass()
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32()
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32()
DSystemZInstrInfo.cpp558 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) || in canInsertSelect()
559 SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in canInsertSelect()
560 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in canInsertSelect()
585 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) { in insertSelect()
600 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in insertSelect()
/openbsd/src/gnu/llvm/llvm/lib/Target/VE/
DVEInstrInfo.cpp497 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
511 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
556 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
568 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp971 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
975 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
979 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
983 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
987 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
991 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
995 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1018 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1021 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1024 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp59 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()
/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/
DAVRRegisterInfo.cpp317 if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()

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