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Searched refs:hasInterval (Results 1 – 19 of 19) sorted by relevance

/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DLiveIntervals.h113 if (hasInterval(Reg)) in getInterval()
123 bool hasInterval(Register Reg) const { in hasInterval() function
130 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
DLiveStacks.h82 bool hasInterval(int Slot) const { return S2IMap.count(Slot); } in hasInterval() function
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DRegAllocBase.cpp147 assert(LIS->hasInterval(Reg)); in allocatePhysRegs()
DLiveIntervals.cpp159 if (hasInterval(Reg)) in print()
1551 if (Reg.isVirtual() && hasInterval(Reg) && !MO.isUndef()) { in handleMoveIntoNewBundle()
1679 if (MO.getSubReg() && hasInterval(Reg) && in repairIntervalsInRange()
1683 if (!hasInterval(Reg)) { in repairIntervalsInRange()
DRenameIndependentSubregs.cpp395 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
DStackSlotColoring.cpp167 if (!LS->hasInterval(FI)) in ScanForSpillSlotRefs()
DLiveRangeEdit.cpp428 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) { in eliminateDeadDef()
DLiveDebugVariables.cpp826 if (!LIS->hasInterval(Reg)) { in handleDebugValue()
1052 if (!LIS.hasInterval(DstReg)) in addDefsFromCopies()
1128 if (LIS.hasInterval(LocMO.getReg())) { in computeIntervals()
DMachineVerifier.cpp2263 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && in visitMachineOperand()
2400 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
2947 if (!LiveInts->hasInterval(Reg)) { in verifyLiveIntervals()
DMachineBasicBlock.cpp1213 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg)) in SplitCriticalEdge()
DInlineSpiller.cpp733 assert(LIS.hasInterval(Reg) && in reMaterializeAll()
DModuloSchedule.cpp348 if (!LIS.hasInterval(ToReg)) in replaceRegUsesAfterLoop()
DRegisterCoalescer.cpp3904 if (!LIS->hasInterval(reg)) in lateLiveIntervalUpdate()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DGCNPreRAOptimizations.cpp229 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
DGCNRegPressure.h225 if (!LIS.hasInterval(Reg)) in getLiveRegMap()
DGCNNSAReassign.cpp225 if (!LIS->hasInterval(Reg)) in CheckNSA()
DGCNRegPressure.cpp240 if (!LIS.hasInterval(Reg)) in getLiveRegs()
DGCNSchedStrategy.cpp1241 if (!DAG.LIS->hasInterval(Reg)) in collectRematerializableInstructions()
DSIRegisterInfo.cpp3066 if (!LIS->hasInterval(Reg)) in findReachingDef()