Searched refs:getSubRegisterClass (Results 1 – 5 of 5) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 644 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass() function
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4226 RI.getSubRegisterClass(RC, MO.getSubReg()); in verifyInstruction()
6851 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6859 RI.getSubRegisterClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6917 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6919 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6985 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6991 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
7005 RI.getSubRegisterClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
7095 RI.getSubRegisterClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
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| D | SIFoldOperands.cpp | 874 TRI->getSubRegisterClass(RC, SubReg)) in foldOperand()
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| D | SIRegisterInfo.cpp | 2909 return getSubRegisterClass(SrcRC, MO.getSubReg()); in getRegClassForOperandReg()
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| D | SIISelLowering.cpp | 4110 TRI->getSubRegisterClass(Src0RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
4112 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
4198 TRI->getSubRegisterClass(Src2RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
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