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Searched refs:getRelaxedOpcode (Results 1 – 5 of 5) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
DARMAsmBackend.h51 unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const;
DARMAsmBackend.cpp209 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op, in getRelaxedOpcode() function in ARMAsmBackend
234 if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode()) in mayNeedRelaxation()
333 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI); in relaxInstruction()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVAsmBackend.h89 unsigned getRelaxedOpcode(unsigned Op) const;
DRISCVAsmBackend.cpp317 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const { in getRelaxedOpcode() function in RISCVAsmBackend
333 return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode(); in mayNeedRelaxation()
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
DX86AsmBackend.cpp229 static unsigned getRelaxedOpcode(const MCInst &Inst, bool Is16BitMode) { in getRelaxedOpcode() function
758 unsigned RelaxedOp = getRelaxedOpcode(Inst, Is16BitMode); in relaxInstruction()
777 return getRelaxedOpcode(Inst, Is16BitMode) == Inst.getOpcode(); in isFullyRelaxed()