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Searched refs:getRegSizeInBits (Results 1 – 25 of 52) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp339 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { in getCommonSuperRegClass()
347 unsigned MinSize = getRegSizeInBits(*RCA); in getCommonSuperRegClass()
355 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
364 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) in getCommonSuperRegClass()
373 if (getRegSizeInBits(*BestRC) == MinSize) in getCommonSuperRegClass()
502 TargetRegisterInfo::getRegSizeInBits(Register Reg, in getRegSizeInBits() function in TargetRegisterInfo
521 return getRegSizeInBits(*RC); in getRegSizeInBits()
DImplicitNullChecks.cpp386 unsigned PointerRegSizeInBits = TRI->getRegSizeInBits(PointerReg, MRI); in isSuitableMemoryOp()
390 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) || in isSuitableMemoryOp()
392 TRI->getRegSizeInBits(ScaledReg, MRI) != PointerRegSizeInBits)) in isSuitableMemoryOp()
423 int32_t RegSizeInBits = TRI->getRegSizeInBits(RegUsedInAddr, MRI); in isSuitableMemoryOp()
DRegisterBank.cpp53 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
DRegisterBankInfo.cpp503 return TRI.getRegSizeInBits(*RC); in getSizeInBits()
505 return TRI.getRegSizeInBits(Reg, MRI); in getSizeInBits()
DMachineVerifier.cpp1865 SrcSize = TRI->getRegSizeInBits(*SrcRC); in visitMachineInstrBefore()
1869 SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); in visitMachineInstrBefore()
1875 DstSize = TRI->getRegSizeInBits(*DstRC); in visitMachineInstrBefore()
1879 DstSize = TRI->getRegSizeInBits(DstReg, *MRI); in visitMachineInstrBefore()
1939 InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI); in visitMachineInstrBefore()
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86RegisterInfo.cpp133 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
140 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
147 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
154 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
168 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
DX86TileConfig.cpp179 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY()
DX86SpeculativeLoadHardening.cpp752 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughCFG()
1181 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughIndirectBranches()
1565 .addImm(TRI->getRegSizeInBits(*PS->RC) - 1); in extractPredStateFromSP()
1868 int RegBytes = TRI->getRegSizeInBits(*RC) / 8; in canHardenRegister()
1916 int Bytes = TRI->getRegSizeInBits(*RC) / 8; in hardenValueInRegister()
2187 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughCall()
/openbsd/src/gnu/llvm/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DGCNRegPressure.cpp44 ? (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) in getRegKind()
46 ? (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) in getRegKind()
47 : (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); in getRegKind()
DSILowerI1Copies.cpp98 TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) == in isLaneMaskReg()
484 unsigned Size = TRI.getRegSizeInBits(Reg, MRI); in isVRegCompatibleReg()
704 assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32); in lowerCopiesToI1()
DSIFixSGPRCopies.cpp856 unsigned MoveSize = TRI->getRegSizeInBits(*SrcRC); in lowerSpecialCase()
894 TRI->getRegSizeInBits(*DstRC)); in analyzeVGPRToSGPRCopy()
1034 size_t SrcSize = TRI->getRegSizeInBits(*SrcRC); in lowerVGPR2SGPRCopies()
1047 int N = TRI->getRegSizeInBits(*SrcRC) / 32; in lowerVGPR2SGPRCopies()
DSIRegisterInfo.cpp2791 unsigned Size = getRegSizeInBits(*SRC); in getEquivalentVGPRClass()
2799 unsigned Size = getRegSizeInBits(*SRC); in getEquivalentAGPRClass()
2807 unsigned Size = getRegSizeInBits(*VRC); in getEquivalentSGPRClass()
2934 unsigned SrcSize = getRegSizeInBits(*SrcRC); in shouldCoalesce()
2935 unsigned DstSize = getRegSizeInBits(*DstRC); in shouldCoalesce()
2936 unsigned NewSize = getRegSizeInBits(*NewRC); in shouldCoalesce()
3112 assert(getRegSizeInBits(*getPhysRegBaseClass(Reg)) <= 32); in get32BitRegister()
3133 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
3135 return RC.hasSuperClassEq(getAGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
3138 getVectorSuperClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
[all …]
DGCNNSAReassign.cpp201 if (TRI->getRegSizeInBits(*MRI->getRegClass(Reg)) != 32 || Op.getSubReg()) in CheckNSA()
DSIInstrInfo.cpp342 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
346 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandsWithOffsetWidth()
725 ((RI.getRegSizeInBits(*RC) == 16) ^ in copyPhysReg()
726 (RI.getRegSizeInBits(*RI.getPhysRegBaseClass(SrcReg)) == 16))) { in copyPhysReg()
727 MCRegister &RegToFix = (RI.getRegSizeInBits(*RC) == 16) ? DestReg : SrcReg; in copyPhysReg()
862 const unsigned Size = RI.getRegSizeInBits(*RC); in copyPhysReg()
1105 if (RI.getRegSizeInBits(*RegClass) > 32) { in materializeImmediate()
1285 if (RI.getRegSizeInBits(*DstRC) == 32) { in getMovOpcode()
1287 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
1289 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
[all …]
DSIShrinkInstructions.cpp316 unsigned Dwords = TRI->getRegSizeInBits(Op.getReg(), *MRI) / 32; in shrinkMIMG()
586 if (TRI->getRegSizeInBits(Reg, *MRI) != 32) { in getSubRegForIndex()
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp390 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
397 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0); in shouldCoalesce()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
DInlineAsmLowering.cpp247 unsigned SrcSize = TRI->getRegSizeInBits(Src, *MRI); in buildAnyextOrCopy()
248 unsigned DstSize = TRI->getRegSizeInBits(Dst, *MRI); in buildAnyextOrCopy()
624 unsigned SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); in lowerInlineAsm()
DInstructionSelect.cpp277 if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) { in runOnMachineFunction()
/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/
DAVRFrameLowering.cpp263 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in spillCalleeSavedRegisters()
300 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in restoreCalleeSavedRegisters()
DAVRAsmPrinter.cpp127 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8; in PrintAsmOperand()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.cpp892 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
893 getRegSizeInBits(*SrcRC) < 256) in shouldCoalesce()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h279 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits() function
848 unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonVExtract.cpp161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp414 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; in printSavedRegsBitmask()
415 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8; in printSavedRegsBitmask()
416 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8; in printSavedRegsBitmask()

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