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Searched refs:dclk (Results 1 – 25 of 54) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/i915/display/
Dintel_bw.c22 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; member
55 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); in dg1_mchbar_read_qgv_point_info()
59 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
61 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
82 u16 dclk; in icl_pcode_read_qgv_point_info() local
91 dclk = val & 0xffff; in icl_pcode_read_qgv_point_info()
92 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
183 u16 dclk; in mtl_read_qgv_point_info() local
189 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); in mtl_read_qgv_point_info()
190 sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); in mtl_read_qgv_point_info()
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/openbsd/src/sys/dev/pci/drm/radeon/
Drs780_dpm.c571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
Dtrinity_dpm.c850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
863 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal()
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1411 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index()
1645 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info()
1648 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1890 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table()
1973 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1998 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
Dsumo_dpm.c822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
839 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_before_set_eng_clock()
857 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_after_set_eng_clock()
1413 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in sumo_parse_pplib_non_clock_info()
1416 rps->dclk = 0; in sumo_parse_pplib_non_clock_info()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
Drv770_dpm.c1441 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1458 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2156 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rv7xx_parse_pplib_non_clock_info()
2159 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2165 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2442 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2486 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
Drv6xx_dpm.c1519 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
Dtrinity_dpm.h69 u32 dclk; member
Dradeon_uvd.c949 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
964 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
985 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, in radeon_uvd_calc_upll_dividers()
991 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
Dradeon_asic.h409 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
476 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
533 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
534 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
748 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
786 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Drv770.c52 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
54 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
61 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
68 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
74 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
Dkv_dpm.c678 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
684 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk); in kv_populate_uvd_table()
693 table->entries[i].dclk, false, &dividers); in kv_populate_uvd_table()
2018 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2392 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in kv_parse_pplib_non_clock_info()
2395 rps->dclk = 0; in kv_parse_pplib_non_clock_info()
2652 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
Dni_dpm.c3516 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock()
3523 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3534 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock()
3541 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3905 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in ni_parse_pplib_non_clock_info()
3908 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in ni_parse_pplib_non_clock_info()
3911 rps->dclk = 0; in ni_parse_pplib_non_clock_info()
4291 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
4319 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_debugfs_print_current_performance_level()
/openbsd/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
Dhwmgr_ppt.h59 uint32_t dclk; /* UVD D-clock */ member
Dsmu10_hwmgr.h98 uint32_t dclk; member
Dsmu8_hwmgr.c525 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0; in smu8_upload_pptable_to_smu()
1439 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry()
1746 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1792 dclk = uvd_table->entries[uvd_index].dclk; in smu8_read_sensor()
1793 *((uint32_t *)value) = dclk; in smu8_read_sensor()
Dsmu8_hwmgr.h115 uint32_t dclk; member
Dsmu7_hwmgr.h69 uint32_t dclk; member
Dvega10_hwmgr.h97 uint32_t dclk; member
Dvega20_hwmgr.h114 uint32_t dclk; member
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Damdgpu_si.c1714 unsigned vclk, unsigned dclk, in si_calc_upll_dividers() argument
1729 vco_min = max(max(vco_min, vclk), dclk); in si_calc_upll_dividers()
1749 dclk_div = si_uvd_calc_upll_post_div(vco_freq, dclk, in si_calc_upll_dividers()
1755 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1775 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in si_set_uvd_clocks() argument
1788 if (!vclk || !dclk) { in si_set_uvd_clocks()
1793 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000, in si_set_uvd_clocks()
Dvi.c1027 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in vi_set_uvd_clocks() argument
1036 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); in vi_set_uvd_clocks()
1044 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in vi_set_uvd_clocks()
Damdgpu_cik.c1481 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in cik_set_uvd_clocks() argument
1489 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in cik_set_uvd_clocks()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/
Ddm_services_types.h66 struct dm_pp_clock_range dclk; member
/openbsd/src/sys/dev/pci/drm/amd/pm/inc/
Damdgpu_dpm.h65 u32 dclk; member
156 u32 dclk; member
/openbsd/src/sys/dev/pci/drm/amd/pm/swsmu/smu12/
Dsmu_v12_0.c393 &smu->smu_table.boot_values.dclk); in smu_v12_0_get_vbios_bootup_values()

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