Searched refs:composeSubRegIndices (Results 1 – 8 of 8) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 350 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
359 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
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| D | RegisterCoalescer.cpp | 427 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in INITIALIZE_PASS_DEPENDENCY()
583 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
584 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable()
1331 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(), in reMaterializeTrivialDef()
1804 unsigned SubUseIdx = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in updateRegDefsUses()
2576 TRI->composeSubRegIndices(SubIdx, MO.getSubReg())); in computeWriteLanes()
3037 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in usesLanes()
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| D | DetectDeadLanes.cpp | 172 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
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| D | TailDuplicator.cpp | 439 MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(), in duplicateInstruction()
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| D | MachineOperand.cpp | 82 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 662 unsigned composeSubRegIndices(unsigned a, unsigned b) const { in composeSubRegIndices() function
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 246 unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx); in getSubOperand64()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 1692 SubRegIdx = TRI->composeSubRegIndices(SubRegIdx, in decomposeSubvectorInsertExtractToSubRegs()
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