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Searched refs:clks (Results 1 – 25 of 28) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0) in dcn20_update_clocks_update_dentist()
140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dentist()
142 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn20_update_clocks_update_dentist()
237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
270 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn2_update_clocks()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c36 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in rv1_init_clocks()
42 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
44 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
74 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
182 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; in ramp_up_dispclk_with_dpp()
183 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; in ramp_up_dispclk_with_dpp()
184 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; in ramp_up_dispclk_with_dpp()
224 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
225 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
226 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c113 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn3_init_clocks()
114 clk_mgr_base->clks.p_state_change_support = true; in dcn3_init_clocks()
115 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn3_init_clocks()
213 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn3_update_clocks()
234 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn3_update_clocks()
235 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn3_update_clocks()
236 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_k… in dcn3_update_clocks()
239 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn3_update_clocks()
240 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn3_update_clocks()
241 …dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_slee… in dcn3_update_clocks()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c93 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_set_low_power_state()
101 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_set_low_power_state()
154 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_update_clocks()
162 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_update_clocks()
167 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in rn_update_clocks()
170 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in rn_update_clocks()
174 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rn_update_clocks()
175 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in rn_update_clocks()
176 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); in rn_update_clocks()
180 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in rn_update_clocks()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce12_update_clocks()
112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dce/
Ddce_clk_mgr.c654 pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
692 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce_update_clocks()
694 clk_mgr->clks.dispclk_khz = patched_disp_clk; in dce_update_clocks()
719 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce11_update_clocks()
721 clk_mgr->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
746 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce112_update_clocks()
748 clk_mgr->clks.dispclk_khz = patched_disp_clk; in dce112_update_clocks()
766 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce12_update_clocks()
776 clk_mgr->clks.dispclk_khz = dce112_set_clock(clk_mgr, patched_disp_clk); in dce12_update_clocks()
781 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) { in dce12_update_clocks()
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/openbsd/src/sys/dev/pci/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c112 struct dm_pp_clock_levels *clks) in get_default_clock_levels() argument
122 clks->num_levels = 6; in get_default_clock_levels()
123 memmove(clks->clocks_in_khz, disp_clks_in_khz, in get_default_clock_levels()
127 clks->num_levels = 6; in get_default_clock_levels()
128 memmove(clks->clocks_in_khz, sclks_in_khz, in get_default_clock_levels()
132 clks->num_levels = 2; in get_default_clock_levels()
133 memmove(clks->clocks_in_khz, mclks_in_khz, in get_default_clock_levels()
137 clks->num_levels = 0; in get_default_clock_levels()
Damdgpu_dm_helpers.c1003 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) in dm_set_dcn_clocks() argument
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/
Ddce60_clk_mgr.c140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks()
142 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce60_update_clocks()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c231 pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce11_update_clocks()
271 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.c211 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce112_update_clocks()
213 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce112_update_clocks()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c417 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce_update_clocks()
419 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce_update_clocks()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/
Ddm_helpers.h179 struct dc_clocks *clks);
/openbsd/src/sys/dev/pci/drm/amd/display/dc/inc/hw/
Dclk_mgr.h329 struct dc_clocks clks; member
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20.c794 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params() local
809 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml20_rq_dlg_get_dlg_params()
810 double dispclk_freq_in_mhz = clks->dispclk_mhz; in dml20_rq_dlg_get_dlg_params()
811 double refclk_freq_in_mhz = clks->refclk_mhz; in dml20_rq_dlg_get_dlg_params()
Ddisplay_rq_dlg_calc_20v2.c794 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params() local
809 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml20v2_rq_dlg_get_dlg_params()
810 double dispclk_freq_in_mhz = clks->dispclk_mhz; in dml20v2_rq_dlg_get_dlg_params()
811 double refclk_freq_in_mhz = clks->refclk_mhz; in dml20v2_rq_dlg_get_dlg_params()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c840 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params() local
855 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml_rq_dlg_get_dlg_params()
856 double dispclk_freq_in_mhz = clks->dispclk_mhz; in dml_rq_dlg_get_dlg_params()
857 double refclk_freq_in_mhz = clks->refclk_mhz; in dml_rq_dlg_get_dlg_params()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c908 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params() local
923 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml_rq_dlg_get_dlg_params()
924 double dispclk_freq_in_mhz = clks->dispclk_mhz; in dml_rq_dlg_get_dlg_params()
925 double refclk_freq_in_mhz = clks->refclk_mhz; in dml_rq_dlg_get_dlg_params()
/openbsd/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
Dsmu8_hwmgr.c769 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold() local
770 if (clks == 0) in smu8_set_deep_sleep_sclk_threshold()
771 clks = SMU8_MIN_DEEP_SLEEP_SCLK; in smu8_set_deep_sleep_sclk_threshold()
773 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks); in smu8_set_deep_sleep_sclk_threshold()
777 clks, in smu8_set_deep_sleep_sclk_threshold()
/openbsd/src/sys/dev/pci/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c697 enum smu_clk_type clks[] = { in renoir_force_dpm_limit_value() enum
703 for (i = 0; i < ARRAY_SIZE(clks); i++) { in renoir_force_dpm_limit_value()
704 clk_type = clks[i]; in renoir_force_dpm_limit_value()
/openbsd/src/sys/dev/pci/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c1283 enum smu_clk_type clks[] = { in vangogh_force_dpm_limit_value() enum
1290 for (i = 0; i < ARRAY_SIZE(clks); i++) { in vangogh_force_dpm_limit_value()
1291 clk_type = clks[i]; in vangogh_force_dpm_limit_value()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/
Ddisplay_mode_vba.c538 display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg; in fetch_pipe_params() local
707 mode_lib->vba.DPPCLK[mode_lib->vba.NumberOfActivePlanes] = clks->dppclk_mhz; in fetch_pipe_params()
/openbsd/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c1132 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in iceland_calculate_mclk_params() local
1141 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks); in iceland_calculate_mclk_params()
Dci_smumgr.c1087 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in ci_calculate_mclk_params() local
1093 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks); in ci_calculate_mclk_params()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/core/
Damdgpu_dc.c2759 …if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.… in dc_check_update_surfaces_for_stream()
2762 …} else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_cl… in dc_check_update_surfaces_for_stream()
5478 funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000; in dc_enable_dcmode_clk_limit()
5479 p_state_change_support = dc->clk_mgr->clks.p_state_change_support; in dc_enable_dcmode_clk_limit()

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