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Searched refs:bw (Results 1 – 25 of 71) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/i915/display/
Dintel_bw.c127 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points; in icl_qgv_points_mask()
128 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; in icl_qgv_points_mask()
409 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max); in icl_get_bw_info()
425 struct intel_bw_info *bi = &dev_priv->display.bw.max[i]; in icl_get_bw_info()
437 int ct, bw; in icl_get_bw_info() local
447 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct); in icl_get_bw_info()
450 bw * (100 - sa->derating) / 100); in icl_get_bw_info()
480 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max); in tgl_get_bw_info()
517 struct intel_bw_info *bi = &dev_priv->display.bw.max[i]; in tgl_get_bw_info()
525 bi_next = &dev_priv->display.bw.max[i + 1]; in tgl_get_bw_info()
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Dintel_dp_tunnel.c62 int bw; in get_current_link_bw() local
64 bw = intel_dp_max_link_data_rate(intel_dp, rate, lane_count); in get_current_link_bw()
65 *below_dprx_bw = bw < drm_dp_max_dprx_data_rate(rate, lane_count); in get_current_link_bw()
67 return bw; in get_current_link_bw()
740 int bw; in atomic_increase_bw() local
750 bw = drm_dp_tunnel_atomic_get_required_bw(tunnel_state); in atomic_increase_bw()
752 if (drm_dp_tunnel_alloc_bw(tunnel, bw) != 0) in atomic_increase_bw()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
Ddcn30_fpu.c371 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
394 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
405 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = in dcn30_fpu_calculate_wm_and_dlg()
408 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
445 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
446 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn30_fpu_calculate_wm_and_dlg()
447 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
448 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn30_fpu_calculate_wm_and_dlg()
449 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
450 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/core/
Ddc_debug.c353 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
354 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
355 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
356 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
357 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
358 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
361 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
362 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
363 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
364 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
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Ddc_link_exports.c291 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw) in dc_link_bw_kbps_from_raw_frl_link_rate_data() argument
293 return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw); in dc_link_bw_kbps_from_raw_frl_link_rate_data()
365 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result) in dc_link_handle_usb4_bw_alloc_response() argument
367 link->dc->link_srv->dpia_handle_bw_alloc_response(link, bw, result); in dc_link_handle_usb4_bw_alloc_response()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
Ddcn20_fpu.c1154 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1157 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1159 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) in dcn20_calculate_dlg_params()
1160 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; in dcn20_calculate_dlg_params()
1162 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
1163 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
1164 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn20_calculate_dlg_params()
1171 …context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_swit… in dcn20_calculate_dlg_params()
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/openbsd/src/usr.bin/ssh/
Dmisc.c1699 bandwidth_limit_init(struct bwlimit *bw, u_int64_t kbps, size_t buflen) in bandwidth_limit_init() argument
1701 bw->buflen = buflen; in bandwidth_limit_init()
1702 bw->rate = kbps; in bandwidth_limit_init()
1703 bw->thresh = buflen; in bandwidth_limit_init()
1704 bw->lamt = 0; in bandwidth_limit_init()
1705 timerclear(&bw->bwstart); in bandwidth_limit_init()
1706 timerclear(&bw->bwend); in bandwidth_limit_init()
1711 bandwidth_limit(struct bwlimit *bw, size_t read_len) in bandwidth_limit() argument
1716 bw->lamt += read_len; in bandwidth_limit()
1717 if (!timerisset(&bw->bwstart)) { in bandwidth_limit()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/dce/
Ddce_clk_mgr.c227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
625 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
629 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
634 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
647 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
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/openbsd/src/sys/dev/ic/
Daac.c749 struct aac_blockwrite *bw; in aac_bio_command() local
750 bw = (struct aac_blockwrite *)&fib->data[0]; in aac_bio_command()
751 bw->Command = VM_CtBlockWrite; in aac_bio_command()
752 bw->ContainerId = xs->sc_link->target; in aac_bio_command()
753 bw->BlockNumber = cm->cm_blkno; in aac_bio_command()
754 bw->ByteCount = cm->cm_bcount * AAC_BLOCK_SIZE; in aac_bio_command()
755 bw->Stable = CUNSTABLE; in aac_bio_command()
758 cm->cm_sgtable = &bw->SgMap; in aac_bio_command()
775 struct aac_blockwrite64 *bw; in aac_bio_command() local
776 bw = (struct aac_blockwrite64 *)&fib->data[0]; in aac_bio_command()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c117 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer_debug.c476 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_get_clock_states()
477 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
478 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
479 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
480 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
481 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_get_clock_states()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
403 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
/openbsd/src/usr.bin/mandoc/
Dtbl_term.c574 int bw; /* Box line width. */ in tbl_hrule() local
590 bw = opts & TBL_OPT_DBOX ? (tp->enc == TERMENC_UTF8 ? 2 : 1) : in tbl_hrule()
592 hw = flags == TBL_OPT_DBOX || flags == TBL_OPT_BOX ? bw : in tbl_hrule()
603 (spp == NULL ? 0 : BUP * bw) + in tbl_hrule()
604 (spn == NULL ? 0 : BDOWN * bw) + in tbl_hrule()
699 (spp == NULL ? 0 : BUP * bw) + in tbl_hrule()
700 (spn == NULL ? 0 : BDOWN * bw) + in tbl_hrule()
/openbsd/src/regress/lib/libcrypto/x509/bettertls/certificates/
D212.key15 DjjrR1FZg9IjZg2yOM7n9aPfbTZhQngBUK08MLrBgGnCO4E/bw/DmScCgYEAsnYA
D3012.key26 p62TBW4PFZyj/05bw/pPU9Knu6qBHSyAEDwsvXf2GbROQFiCYHWKjg==
D321.chain46 Js/pG+3ObRjE8y0/AmSp7u3+5k6JsV3436gT3GQkQeC/znkFVSRXHaUcz/bw
D3047.chain35 nDKuwAYcnbUDt73rft1rCS5HnDQcEmwag5VGRdBX4oaJcY7pl8/Et5l4fTmEo+bw
D955.chain46 5VbM+8pOlE8/bw==
D247.chain41 y7U+xe6CDPm81nW8J9zqMWA/bw/GF8YPlnY7KzDXNujGQA5DS6Yt+H0HH5icrCh/
/openbsd/src/gnu/usr.bin/perl/Porting/
DcheckURL.pl76 my $bw = Parallel::Fork::BossWorkerAsync->new(
84 $bw->add_work( { uri => $uri, filenames => \@filenames } );
96 while ( $bw->pending() ) {
97 my $response = $bw->get_result();
111 $bw->shut_down();
/openbsd/src/usr.bin/aucat/
Dafile.c36 unsigned char bw[2]; member
191 return p->bw[1] | p->bw[0] << 8; in be16_get()
197 p->bw[1] = v; in be16_set()
198 p->bw[0] = v >> 8; in be16_set()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/inc/
Dlink.h210 uint32_t (*bw_kbps_from_raw_frl_link_rate_data)(uint8_t bw);
220 struct dc_link *link, uint8_t bw, uint8_t result);
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86InstrExtension.td40 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>,
44 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>,
66 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>,
70 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>,
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c91 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()

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