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Searched refs:addReg (Results 1 – 25 of 286) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp159 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
160 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
161 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
165 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
166 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
167 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
193 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
194 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
195 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
202 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCExpandAtomicPseudoInsts.cpp59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
67 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
162 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
171 .addReg(IncrLo) in expandAtomicRMW128()
172 .addReg(OldLo); in expandAtomicRMW128()
[all …]
DPPCReturnProtectorLowering.cpp68 .addReg(TOCReg) in insertReturnProtectorPrologue()
72 .addReg(REG); in insertReturnProtectorPrologue()
75 .addReg(REG) in insertReturnProtectorPrologue()
76 .addReg(LRReg); in insertReturnProtectorPrologue()
83 .addReg(LRReg, RegState::Define) in insertReturnProtectorPrologue()
87 .addReg(REG) in insertReturnProtectorPrologue()
91 .addReg(REG); in insertReturnProtectorPrologue()
95 .addReg(REG); in insertReturnProtectorPrologue()
98 .addReg(REG) in insertReturnProtectorPrologue()
99 .addReg(LRReg); in insertReturnProtectorPrologue()
[all …]
DPPCFrameLowering.cpp797 MIB.addReg(MustSaveCRs[0], RegState::Kill); in emitPrologue()
802 MIB.addReg(CRfield, RegState::ImplicitKill); in emitPrologue()
811 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
813 .addReg(SPReg); in emitPrologue()
825 .addReg(FPReg) in emitPrologue()
827 .addReg(SPReg); in emitPrologue()
830 .addReg(PPC::R30) in emitPrologue()
832 .addReg(SPReg); in emitPrologue()
835 .addReg(BPReg) in emitPrologue()
837 .addReg(SPReg); in emitPrologue()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVAsmPrinter.cpp304 MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8), in EmitHwasanMemaccessSymbols()
307 .addReg(RISCV::X6) in EmitHwasanMemaccessSymbols()
308 .addReg(RISCV::X6) in EmitHwasanMemaccessSymbols()
313 .addReg(RISCV::X6) in EmitHwasanMemaccessSymbols()
314 .addReg(RISCV::X5) in EmitHwasanMemaccessSymbols()
315 .addReg(RISCV::X6), in EmitHwasanMemaccessSymbols()
318 MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0), in EmitHwasanMemaccessSymbols()
322 MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56), in EmitHwasanMemaccessSymbols()
328 .addReg(RISCV::X7) in EmitHwasanMemaccessSymbols()
329 .addReg(RISCV::X6) in EmitHwasanMemaccessSymbols()
[all …]
DRISCVExpandAtomicPseudoInsts.cpp234 .addReg(AddrReg); in doAtomicBinOpExpansion()
240 .addReg(DestReg) in doAtomicBinOpExpansion()
241 .addReg(IncrReg); in doAtomicBinOpExpansion()
243 .addReg(ScratchReg) in doAtomicBinOpExpansion()
248 .addReg(AddrReg) in doAtomicBinOpExpansion()
249 .addReg(ScratchReg); in doAtomicBinOpExpansion()
251 .addReg(ScratchReg) in doAtomicBinOpExpansion()
252 .addReg(RISCV::X0) in doAtomicBinOpExpansion()
268 .addReg(OldValReg) in insertMaskedMerge()
269 .addReg(NewValReg); in insertMaskedMerge()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsExpandPseudo.cpp145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
147 .addReg(Scratch) in expandAtomicCmpSwapSubword()
148 .addReg(Mask); in expandAtomicCmpSwapSubword()
150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB); in expandAtomicCmpSwapSubword()
158 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
159 .addReg(Mask2); in expandAtomicCmpSwapSubword()
161 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
162 .addReg(ShiftNewVal); in expandAtomicCmpSwapSubword()
164 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
165 .addReg(Ptr) in expandAtomicCmpSwapSubword()
[all …]
DMipsReturnProtectorLowering.cpp63 .addReg(TempReg1) in insertReturnProtectorPrologue()
64 .addReg(Mips::T9_64); in insertReturnProtectorPrologue()
66 .addReg(TempReg2) in insertReturnProtectorPrologue()
69 .addReg(TempReg1) in insertReturnProtectorPrologue()
70 .addReg(TempReg2); in insertReturnProtectorPrologue()
72 .addReg(TempReg1) in insertReturnProtectorPrologue()
75 .addReg(REG) in insertReturnProtectorPrologue()
85 .addReg(TempReg1) in insertReturnProtectorPrologue()
88 .addReg(TempReg1) in insertReturnProtectorPrologue()
91 .addReg(TempReg1) in insertReturnProtectorPrologue()
[all …]
DMipsFastISel.cpp217 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
222 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
328 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
365 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
368 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
377 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
392 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
400 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
418 .addReg(MFI->getGlobalBaseReg(*MF)) in materializeGV()
424 .addReg(DestReg) in materializeGV()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
116 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp183 .addReg(TIP.first) in runOnMachineFunction()
186 .addReg(0)); in runOnMachineFunction()
1047 .addReg(0)); in emitJumpTableInsts()
1378 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
1382 .addReg(MI->getOperand(3).getReg())); in emitInstruction()
1394 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
1398 .addReg(MI->getOperand(3).getReg())); in emitInstruction()
1405 .addReg(ARM::LR) in emitInstruction()
1406 .addReg(ARM::PC) in emitInstruction()
1409 .addReg(0) in emitInstruction()
[all …]
DARMExpandPseudoInsts.cpp605 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
609 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
611 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
613 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
615 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
677 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
738 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
740 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
742 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
744 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86InstrBuilder.h127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
177 MIB.addReg(AM.Base.Reg); in addFullAddress()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
189 return MIB.addReg(0); in addFullAddress()
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
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DX86ReturnProtectorLowering.cpp42 .addReg(X86::RIP) in insertReturnProtectorPrologue()
44 .addReg(0) in insertReturnProtectorPrologue()
46 .addReg(0); in insertReturnProtectorPrologue()
47 addDirectMem(BuildMI(MBB, MI, MBBDL, TII->get(X86::XOR64rm), REG).addReg(REG), in insertReturnProtectorPrologue()
59 addDirectMem(BuildMI(MBB, MI, MBBDL, TII->get(X86::XOR64rm), REG).addReg(REG), in insertReturnProtectorEpilogue()
62 .addReg(REG) in insertReturnProtectorEpilogue()
63 .addReg(X86::RIP) in insertReturnProtectorEpilogue()
65 .addReg(0) in insertReturnProtectorEpilogue()
67 .addReg(0); in insertReturnProtectorEpilogue()
/openbsd/src/gnu/llvm/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg) in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/VE/
DVEFrameLowering.cpp153 .addReg(VE::SX11) in emitPrologueInsns()
156 .addReg(VE::SX9); in emitPrologueInsns()
158 .addReg(VE::SX11) in emitPrologueInsns()
161 .addReg(VE::SX10); in emitPrologueInsns()
165 .addReg(VE::SX11) in emitPrologueInsns()
168 .addReg(VE::SX15); in emitPrologueInsns()
170 .addReg(VE::SX11) in emitPrologueInsns()
173 .addReg(VE::SX16); in emitPrologueInsns()
177 .addReg(VE::SX11) in emitPrologueInsns()
180 .addReg(VE::SX17); in emitPrologueInsns()
[all …]
DVERegisterInfo.cpp214 build(VE::ANDrm, clobber).addReg(clobber).addImm(M0(32)); in prepareReplaceFI()
216 .addReg(clobber) in prepareReplaceFI()
217 .addReg(FrameReg) in prepareReplaceFI()
248 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(SrcLoReg); in processSTQ()
269 build(VE::LDrii, DestLoReg).addReg(FrameReg).addImm(0).addImm(0); in processLDQ()
302 build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i); in processSTVM()
304 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg( in processSTVM()
309 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
341 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0); in processLDVM()
352 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64SIMDInstrOpt.cpp450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
455 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
456 .addReg(DupDest, Src2IsKill); in optimizeVectElement()
462 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
467 .addReg(DupDest, Src1IsKill); in optimizeVectElement()
566 .addReg(StReg[0]) in optimizeLdStInterleave()
567 .addReg(StReg[1]); in optimizeLdStInterleave()
569 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
[all …]
DAArch64AsmPrinter.cpp341 .addReg(AddrReg) in LowerKCFI_CHECK()
342 .addReg(AArch64::XZR) in LowerKCFI_CHECK()
343 .addReg(AArch64::XZR) in LowerKCFI_CHECK()
370 .addReg(ScratchRegs[0]) in LowerKCFI_CHECK()
371 .addReg(AddrReg) in LowerKCFI_CHECK()
378 .addReg(ScratchRegs[1]) in LowerKCFI_CHECK()
379 .addReg(ScratchRegs[1]) in LowerKCFI_CHECK()
383 .addReg(ScratchRegs[1]) in LowerKCFI_CHECK()
384 .addReg(ScratchRegs[1]) in LowerKCFI_CHECK()
390 .addReg(AArch64::WZR) in LowerKCFI_CHECK()
[all …]
DAArch64ReturnProtectorLowering.cpp45 .addReg(REG) in insertReturnProtectorPrologue()
48 .addReg(REG) in insertReturnProtectorPrologue()
49 .addReg(AArch64::LR); in insertReturnProtectorPrologue()
65 .addReg(REG) in insertReturnProtectorEpilogue()
66 .addReg(AArch64::LR); in insertReturnProtectorEpilogue()
70 .addReg(AArch64::X9) in insertReturnProtectorEpilogue()
73 .addReg(REG) in insertReturnProtectorEpilogue()
74 .addReg(AArch64::X9); in insertReturnProtectorEpilogue()
75 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::RETGUARD_JMP_TRAP)).addReg(REG); in insertReturnProtectorEpilogue()
/openbsd/src/gnu/llvm/llvm/tools/llvm-exegesis/lib/PowerPC/
DTarget.cpp62 .addReg(Reg) in loadImmediate()
104 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
110 MCInstBuilder(PPC::MTVRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
114 .addReg(Reg) in setRegTo()
115 .addReg(ScratchImmReg) in setRegTo()
116 .addReg(ScratchImmReg)}; in setRegTo()
119 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
/openbsd/src/gnu/llvm/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp71 .addReg(FrameReg) in InsertFPImmInst()
77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
78 .addReg(FrameReg) in InsertFPImmInst()
84 .addReg(FrameReg) in InsertFPImmInst()
107 .addReg(FrameReg) in InsertFPConstInst()
108 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
114 .addReg(FrameReg) in InsertFPConstInst()
115 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
120 .addReg(FrameReg) in InsertFPConstInst()
[all …]
/openbsd/src/gnu/llvm/llvm/tools/llvm-exegesis/lib/Mips/
DTarget.cpp90 .addReg(Reg) in loadImmediate()
91 .addReg(ZeroReg) in loadImmediate()
103 .addReg(Reg) in loadImmediate()
104 .addReg(ZeroReg) in loadImmediate()
108 .addReg(Reg) in loadImmediate()
109 .addReg(Reg) in loadImmediate()
114 .addReg(Reg) in loadImmediate()
122 .addReg(Reg) in loadImmediate()
123 .addReg(ZeroReg) in loadImmediate()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp648 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
651 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
657 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
659 .addReg(P.first); in splitMemRef()
661 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
663 .addReg(P.second); in splitMemRef()
675 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
741 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
749 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
767 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg()); in splitExt()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp165 .addReg(SrcReg); in selectCOPY()
168 .addReg(MaskedReg); in selectCOPY()
249 .addReg(Reg, 0, ComposedSubIdx); in getSubOperand64()
385 .addReg(CarryReg, RegState::Kill) in selectG_ADD_SUB()
393 .addReg(DstLo) in selectG_ADD_SUB()
395 .addReg(DstHi) in selectG_ADD_SUB()
433 .addReg(I.getOperand(4).getReg()); in selectG_UADDO_USUBO_UADDE_USUBE()
443 .addReg(AMDGPU::SCC); in selectG_UADDO_USUBO_UADDE_USUBE()
520 .addReg(SrcReg, 0, SubReg); in selectG_EXTRACT()
564 .addReg(copyToVGPRIfSrcFolded(Src0, Src0Mods, I.getOperand(1), &I)) in selectG_FMA_FMAD()
[all …]

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