Searched refs:__u64 (Results 1 – 14 of 14) sorted by relevance
66 __u64 ring_base_address; /* to KFD */67 __u64 write_pointer_address; /* from KFD */68 __u64 read_pointer_address; /* from KFD */69 __u64 doorbell_offset; /* from KFD */78 __u64 eop_buffer_address; /* to KFD */79 __u64 eop_buffer_size; /* to KFD */80 __u64 ctx_save_restore_address; /* to KFD */93 __u64 ring_base_address; /* to KFD */104 __u64 cu_mask_ptr; /* to KFD */108 __u64 ctl_stack_address; /* to KFD */[all …]
58 __u64 tx_ts;59 __u64 rx_ts;490 __u64 ts;
108 __u64 next_extension;289 (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \290 ((__u64)(gt) << __I915_PMU_GT_SHIFT))548 …ne DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)899 __u64 addr;907 __u64 gtt_start;912 __u64 gtt_end;921 __u64 size;936 __u64 offset;938 __u64 size;[all …]
179 __u64 bo_size;181 __u64 alignment;183 __u64 domains;185 __u64 domain_flags;216 __u64 bo_info_ptr;304 __u64 flags;334 __u64 flags;370 __u64 addr;371 __u64 size;424 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)[all …]
263 __u64 fb_id_ptr;264 __u64 crtc_id_ptr;265 __u64 connector_id_ptr;266 __u64 encoder_id_ptr;278 __u64 set_connectors_ptr;357 __u64 format_type_ptr;361 __u64 plane_id_ptr;460 __u64 encoders_ptr;462 __u64 modes_ptr;464 __u64 props_ptr;[all …]
65 typedef uint64_t __u64; typedef628 __u64 size;790 __u64 capability;791 __u64 value;883 __u64 capability;884 __u64 value;923 __u64 src_point;924 __u64 dst_point;934 __u64 handles;948 __u64 deadline_nsec;[all …]
800 __u64 gart_size;801 __u64 vram_size;802 __u64 vram_visible;814 __u64 size;815 __u64 alignment;832 __u64 addr;833 __u64 size;871 __u64 offset;872 __u64 size;873 __u64 addr_ptr;[all …]
436 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))964 static inline __u64965 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) in drm_fourcc_canonicalize_nvidia_format_mod()1019 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))1137 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))1604 ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)1608 (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
36 __u64 start;37 __u64 start_gpa;38 __u64 drm_format_mod;
11 typedef unsigned long __u64; typedef20 __u64 irq_and_bh_counts;35 __u64 bytes;
203 static inline __u64 drm_vma_node_offset_addr(struct drm_vma_offset_node *node) in drm_vma_node_offset_addr()205 return ((__u64)node->vm_node.start) << PAGE_SHIFT; in drm_vma_node_offset_addr()
22 typedef uint64_t __u64; typedef
822 __u64 hdr_mult;
88 static inline struct fixed31_32 amdgpu_dm_fixpt_from_s3132(__u64 x) in amdgpu_dm_fixpt_from_s3132()