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Searched refs:__SHIFTIN (Results 1 – 7 of 7) sorted by relevance

/openbsd/src/sys/dev/pci/
Dif_et.c76 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) macro
315 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | in et_miibus_readreg()
316 __SHIFTIN(reg, ET_MII_ADDR_REG); in et_miibus_readreg()
358 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | in et_miibus_writereg()
359 __SHIFTIN(reg, ET_MII_ADDR_REG); in et_miibus_writereg()
363 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE)); in et_miibus_writereg()
396 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN); in et_miibus_statchg()
893 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | in et_chip_attach()
894 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | in et_chip_attach()
895 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | in et_chip_attach()
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Dif_aq_pci.c603 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) macro
619 _v |= __SHIFTIN((val), (mask)); \
/openbsd/src/sys/dev/ic/
Dbcmgenet.c119 __SHIFTIN(phy, GENET_MDIO_PMD) | in genet_mii_readreg()
120 __SHIFTIN(reg, GENET_MDIO_REG)); in genet_mii_readreg()
140 __SHIFTIN(phy, GENET_MDIO_PMD) | in genet_mii_writereg()
141 __SHIFTIN(reg, GENET_MDIO_REG)); in genet_mii_writereg()
179 val |= __SHIFTIN(speed, GENET_UMAC_CMD_SPEED); in genet_update_link()
197 status = flags | __SHIFTIN(len, GENET_TX_DESC_STATUS_BUFLEN); in genet_setup_txdesc()
533 __SHIFTIN(TX_DESC_COUNT, GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT) | in genet_init_rings()
534 __SHIFTIN(MCLBYTES, GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH)); in genet_init_rings()
566 __SHIFTIN(RX_DESC_COUNT, GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT) | in genet_init_rings()
567 __SHIFTIN(MCLBYTES, GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH)); in genet_init_rings()
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Dbwi.c1107 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | in bwi_mac_init()
1108 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); in bwi_mac_init()
1268 state_lo &= ~__SHIFTIN(BWI_STATE_LO_FLAG_PHYRST, in bwi_mac_reset()
1329 __SHIFTIN(tpctl->tp_ctrl1, BWI_RFR_TXPWR1_MASK)); in bwi_mac_set_tpctl_11bg()
2906 __SHIFTIN(bbp_atten, mask)); in bwi_phy_set_bbp_atten()
2913 __SHIFTIN(bbp_atten, mask)); in bwi_phy_set_bbp_atten()
5730 thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) | in bwi_rf_set_nrssi_thr_11g()
5731 __SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK); in bwi_rf_set_nrssi_thr_11g()
5747 val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) | in bwi_rf_clear_tssi()
5748 __SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK); in bwi_rf_clear_tssi()
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Dbcmgenetreg.h42 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) macro
Dbwireg.h700 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) macro
/openbsd/src/sys/dev/fdt/
Dif_mvnetareg.h425 #define MVNETA_PTFUT_IPGINTTX_V1(x) __SHIFTIN(x, MVNETA_PTFUT_IPGINTTX_V1_MASK)
426 #define MVNETA_PTFUT_IPGINTTX_V2(x) __SHIFTIN(x, MVNETA_PTFUT_IPGINTTX_V2_MASK)