Home
last modified time | relevance | path

Searched refs:_MASKED_BIT_ENABLE (Results 1 – 20 of 20) sorted by relevance

/openbsd/src/sys/dev/pci/drm/i915/
Dintel_clock_gating.c445 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in bdw_init_clock_gating()
507 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
511 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
513 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
547 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in vlv_init_clock_gating()
582 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in chv_init_clock_gating()
628 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); in i965gm_init_clock_gating()
640 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); in i965g_init_clock_gating()
653 _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); in gen3_init_clock_gating()
660 intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
[all …]
Di915_reg_defs.h204 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro
Di915_perf.c2848 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen8_enable_metric_set()
2891 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); in gen12_enable_metric_set()
2893 _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING)); in gen12_enable_metric_set()
2898 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen12_enable_metric_set()
4531 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); in mask_reg_value()
4538 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); in mask_reg_value()
Dintel_uncore.c125 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
/openbsd/src/sys/dev/pci/drm/i915/gvt/
Dreg.h94 (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
Dmmio_context.c474 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in is_inhibit_context()
Dhandlers.c2025 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); in ring_mode_mmio_write()
2028 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); in ring_mode_mmio_write()
2130 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); in csfe_chicken1_mmio_write()
2511 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
/openbsd/src/sys/dev/pci/drm/i915/gt/
Dintel_rc6.c387 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in chv_rc6_enable()
412 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in vlv_rc6_enable()
772 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
782 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
Dintel_ggtt_fencing.c921 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in intel_gt_init_swizzling()
925 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in intel_gt_init_swizzling()
929 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in intel_gt_init_swizzling()
Dintel_ring_submission.c127 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in flush_cs_tlb()
171 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in set_pp_dir()
687 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); in load_pd_dir()
736 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
1023 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in gen6_bsd_submit_request()
Dintel_workarounds.c301 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
307 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_mcr_masked_en()
651 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), in icl_ctx_workarounds_init()
1100 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), in hsw_gt_workarounds_init()
2241 _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES), in rcs_engine_wa_init()
2647 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), in rcs_engine_wa_init()
2663 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), in rcs_engine_wa_init()
2863 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), in general_render_compute_wa_init()
Dintel_lrc.c846 ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH); in init_common_regs()
854 ctl |= _MASKED_BIT_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE); in init_common_regs()
1347 *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE); in gen12_invalidate_state_cache()
Dintel_engine_cs.c1243 engine->tlb_inv.request = _MASKED_BIT_ENABLE(val); in intel_engine_init_tlb_invalidation()
1638 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); in __intel_engine_stop_cs()
1646 _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); in __intel_engine_stop_cs()
2564 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); in xehp_enable_ccs_engines()
Dgen6_ppgtt.c70 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
Dintel_reset.c592 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); in gen8_engine_reset_prepare()
Dintel_execlists_submission.c2945 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE); in enable_execlists()
2947 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE); in enable_execlists()
/openbsd/src/sys/dev/pci/drm/i915/gt/uc/
Dintel_uc_fw.c1120 _MASKED_BIT_ENABLE(dma_flags | START_DMA)); in uc_fw_xfer()
Dintel_guc_submission.c4387 _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); in start_engine()
/openbsd/src/sys/dev/pci/drm/i915/display/
Dintel_display_irq.c1295 intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); in i915gm_enable_vblank()
Di9xx_wm.c161 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()
172 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : in _intel_set_memory_cxsr()