Searched refs:XCHG (Results 1 – 17 of 17) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/Transforms/Instrumentation/ |
| D | MemProfiler.cpp | 296 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in isInterestingMemoryAccess() local
300 Access.AccessTy = XCHG->getCompareOperand()->getType(); in isInterestingMemoryAccess()
301 Access.Addr = XCHG->getPointerOperand(); in isInterestingMemoryAccess()
|
| D | HWAddressSanitizer.cpp | 760 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in getInterestingMemoryOperands() local
761 if (!ClInstrumentAtomics || ignoreAccess(I, XCHG->getPointerOperand())) in getInterestingMemoryOperands()
763 Interesting.emplace_back(I, XCHG->getPointerOperandIndex(), true, in getInterestingMemoryOperands()
764 XCHG->getCompareOperand()->getType(), in getInterestingMemoryOperands()
784 if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) in getPointerOperandIndex() local
785 return XCHG->getPointerOperandIndex(); in getPointerOperandIndex()
|
| D | AddressSanitizer.cpp | 1322 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in getInterestingMemoryOperands() local
1323 if (!ClInstrumentAtomics || ignoreAccess(I, XCHG->getPointerOperand())) in getInterestingMemoryOperands()
1325 Interesting.emplace_back(I, XCHG->getPointerOperandIndex(), true, in getInterestingMemoryOperands()
1326 XCHG->getCompareOperand()->getType(), in getInterestingMemoryOperands()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86FixupGadgets.cpp | 610 unsigned XCHG = Is64Bit ? X86::XCHG64rr : X86::XCHG32rr; in fixupInstruction() local
648 BuildMI(MBB, MI, DL, TII->get(XCHG)) in fixupInstruction()
671 BuildMI(MBB, ++MachineBasicBlock::instr_iterator(MI), DL, TII->get(XCHG)) in fixupInstruction()
|
| D | X86ScheduleZnver2.td | 526 // XCHG.
532 def : InstRW<[Zn2WriteXCHG], (instregex "^XCHG(8|16|32|64)rr", "^XCHG(16|32|64)ar")>;
539 def : InstRW<[Zn2WriteXCHGrm, ReadAfterLd], (instregex "^XCHG(8|16|32|64)rm")>;
|
| D | X86ScheduleZnver1.td | 527 // XCHG.
533 def : InstRW<[ZnWriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>;
|
| D | X86ScheduleAtom.td | 624 "XCHG(8|16|32|64)rm",
|
| D | X86ScheduleBtVer2.td | 460 // atomic XCHG operations. We need two writes because the instruction latency
|
| D | X86SchedSkylakeClient.td | 1311 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
|
| D | X86SchedBroadwell.td | 1154 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
|
| D | X86SchedHaswell.td | 1315 def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
|
| D | X86SchedAlderlakeP.td | 2368 def : InstRW<[ADLPWriteResGroup273, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
|
| D | X86SchedSkylakeServer.td | 1839 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
|
| D | X86SchedIceLake.td | 1859 def: InstRW<[ICXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
|
| D | X86InstrInfo.td | 2134 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable;
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 751 class XCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
790 def XCHGD : XCHG<BPF_DW, "64", atomic_swap_64>;
|
| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | Atomics.rst | 437 generate an ``XCHG``, other stores generate a ``MOV``. SequentiallyConsistent
440 uses ``XCHG``, ``atomicrmw add`` and ``atomicrmw sub`` use ``XADD``, and all
|