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Searched refs:Vn (Results 1 – 19 of 19) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMInstrNEON.td2623 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2624 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2625 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2627 let TwoOperandAliasConstraint = "$Vn = $Vd";
2636 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2637 OpcodeStr, "$Vd, $Vn, $Vm", "",
2638 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2640 let TwoOperandAliasConstraint = "$Vn = $Vd";
2648 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2649 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
[all …]
DARMInstrCDE.td430 iname#"\t$coproc, $Vd, $Vn, $Vm, $imm", params.Cstr> {
444 bits<5> Vn;
447 let Inst{19-16} = Vn{4-1};
449 let Inst{7} = Vn{0};
460 bits<5> Vn;
463 let Inst{19-16} = Vn{3-0};
465 let Inst{7} = Vn{4};
475 let Rn = (ins regclass:$Vn);
DARMInstrFormats.td2439 bits<5> Vn;
2444 let Inst{19-16} = Vn{3-0};
2445 let Inst{7} = Vn{4};
2454 Dt, "$Vd, $Vn, $Vm", "", pattern> {
2456 bits<5> Vn;
2462 let Inst{19-16} = Vn{3-0};
2463 let Inst{7} = Vn{4};
2484 bits<5> Vn;
2490 let Inst{19-16} = Vn{3-0};
2491 let Inst{7} = Vn{4};
[all …]
/openbsd/src/regress/lib/libcrypto/x509/bettertls/certificates/
D2844.key7 Vn/bqyWnlZfyhN+fDnN32uzz6xn6IRDt0cDjZQIDAQABAoIBAQCdCT9BcfyOwEc3
D885.chain43 Vn+zu2P0lMydzdyd/QlCqegza9PklLBifjej6+EuRFHAWZJyZGzuX7uj77xKqLAE
D1326.chain13 /8Vn+uZN3jeQ8sMSgvUqI+8yKfCLLpIb7YdrqvC+HDTmpEOo6eZ8djH6ign22SVE
D2636.chain15 juMC1qrHZIyOYnwtZUIVx0L09QoIOWb36YAnOaHtbiL7MU/NHlOb/fHjcU7+Vn/k
D3609.chain45 6uzGxj3OmwW/Uh3/Vn+kN6DyCt/v+VVaOjU4KFS0rcv6fDvgNZm0SYleuLL8TtGh
D3425.chain43 mOb0a9h4XNJ/00Vn+BRtfh/laEgGcf6j3wTEI7+2RiaiUc6pen1MaEzBKaW0pzxo
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1159 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))),
1160 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>;
1162 def : Pat<(v2i64 (int_aarch64_crypto_sha512su0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
1163 (SHA512SU0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
1175 : Pat<(xor (xor (VecTy V128:$Vn), (VecTy V128:$Vm)), (VecTy V128:$Va)),
1176 (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
1184 : Pat<(xor (VecTy V128:$Vn), (and (VecTy V128:$Vm), (vnot (VecTy V128:$Va)))),
1185 (BCAX (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
1207 def : Pat<(v2i64 (int_aarch64_crypto_rax1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
1208 (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
[all …]
DAArch64InstrFormats.td6442 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
6443 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
6444 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
6445 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
6447 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
6448 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
6449 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
6450 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
6451 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
6452 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
[all …]
DAArch64SchedCyclone.td336 // ORR.16b Vd,Vn,Vn
DSVEInstrFormats.td6813 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
6814 asm, "\t$Zd, $Pg/m, $Vn",
6818 bits<5> Vn;
6824 let Inst{9-5} = Vn;
6838 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
6839 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
6840 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
6841 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
6842 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
6843 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
[all …]
/openbsd/src/gnu/llvm/llvm/docs/
DAMDGPUOperandSyntax.rst94 **[Vm**, \ **Vn**, ... **Vk**\ **]** A sequence of 32-bit *vector* registers.
/openbsd/src/gnu/gcc/gcc/doc/
Dtree-ssa.texi1668 may-aliases(T) = @{ V1, V2, V3, ..., Vn @}
1680 may-aliases(Vn) = @{ T @}
Dgccint.info7837 may-aliases(T) = { V1, V2, V3, ..., Vn }
7847 may-aliases(Vn) = { T }
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp6133 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); in DecodeNEONComplexLane64Instruction() local
6134 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); in DecodeNEONComplexLane64Instruction()
6148 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) in DecodeNEONComplexLane64Instruction()
/openbsd/src/gnu/usr.bin/perl/t/re/
Dre_tests1864 \Vn \xFFn/ y $& \xFFn
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td173 // bits<5> Vn : vector register input or output for operand n