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Searched refs:VecRC (Results 1 – 6 of 6) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonVExtract.cpp139 const auto &VecRC = *MRI.getRegClass(VecR); in runOnMachineFunction() local
140 Align Alignment = HRI.getSpillAlign(VecRC); in runOnMachineFunction()
146 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment, in runOnMachineFunction()
152 unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID in runOnMachineFunction()
161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
DHexagonVLIWPacketizer.cpp877 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF); in canPromoteToDotNew() local
878 if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass) in canPromoteToDotNew()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3327 const TargetRegisterClass *VecRC = nullptr; in emitINSERT_DF_VIDX() local
3343 VecRC = &Mips::MSA128BRegClass; in emitINSERT_DF_VIDX()
3349 VecRC = &Mips::MSA128HRegClass; in emitINSERT_DF_VIDX()
3355 VecRC = &Mips::MSA128WRegClass; in emitINSERT_DF_VIDX()
3361 VecRC = &Mips::MSA128DRegClass; in emitINSERT_DF_VIDX()
3366 Register Wt = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3384 Register WdTmp1 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3390 Register WdTmp2 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp3021 const TargetRegisterClass *VecRC = in selectG_INSERT_VECTOR_ELT() local
3026 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
3027 !RBI.constrainGenericRegister(DstReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
3036 std::tie(IdxReg, SubReg) = computeIndirectRegIndex(*MRI, TRI, VecRC, IdxReg, in selectG_INSERT_VECTOR_ELT()
3060 TII.getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false); in selectG_INSERT_VECTOR_ELT()
DSIISelLowering.cpp3826 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg); in emitIndirectSrc() local
3831 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset); in emitIndirectSrc()
3847 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true); in emitIndirectSrc()
3882 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true); in emitIndirectSrc()
3912 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst() local
3919 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC, in emitIndirectDst()
3948 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false); in emitIndirectDst()
3958 TRI.getRegSizeInBits(*VecRC), 32, false); in emitIndirectDst()
3974 Register PhiReg = MRI.createVirtualRegister(VecRC); in emitIndirectDst()
3983 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false); in emitIndirectDst()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp4127 const TargetRegisterClass *VecRC = in emitExtractVectorElt() local
4129 if (!VecRC) { in emitExtractVectorElt()