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Searched refs:VPR (Results 1 – 14 of 14) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DMVEVPTBlockPass.cpp75 if (CmpMI->modifiesRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
77 if (CmpMI->readsRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
135 if (Iter->definesRegister(ARM::VPR) || Iter->killsRegister(ARM::VPR)) in IsVPRDefinedOrKilledByBlock()
DMVETPAndVPTOptimisationsPass.cpp931 Register VPR = Instr.getOperand(PIdx + 1).getReg(); in ReplaceConstByVPNOTs() local
932 if (!VPR.isVirtual()) in ReplaceConstByVPNOTs()
936 MachineInstr *Copy = MRI->getVRegDef(VPR); in ReplaceConstByVPNOTs()
960 if (LastVPTReg != 0 && LastVPTReg != VPR && LastVPTImm == Imm) { in ReplaceConstByVPNOTs()
962 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
979 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
986 VPR = NewVPR; in ReplaceConstByVPNOTs()
990 LastVPTReg = VPR; in ReplaceConstByVPNOTs()
DARMLowOverheadLoops.cpp91 return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR; in isVectorPredicated()
95 return MI->findRegisterDefOperandIdx(ARM::VPR) != -1; in isVectorPredicate()
99 return MI.findRegisterUseOperandIdx(ARM::VPR) != -1; in hasVPRUse()
204 assert((CurrentPredicates.size() || MI->getParent()->isLiveIn(ARM::VPR)) in CreateVPTBlock()
1042 if (RegMask.PhysReg == ARM::VPR) { in ValidateLiveOuts()
1254 if (!MO.isReg() || !MO.isUse() || MO.getReg() != ARM::VPR) in ValidateMVEInst()
1697 MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR); in ConvertVPTBlocks()
DARMRegisterInfo.td203 // on the instruction they are used in and for VPR 32 was chosen such that it
205 def VPR : ARMReg<32, "vpr">;
400 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> {
458 // Scalar single and double precision floating point and VPR register class,
461 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
DARMInstrVFP.td326 let Defs = [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, VPR, FPSCR, FPSCR_NZCV];
2523 // System level VPR/P0 -> GPR
2524 let Uses = [VPR] in
2594 // System level GPR -> VPR/P0
2595 let Defs = [VPR] in
2883 let Uses = [VPR] in {
2889 let Defs = [VPR] in {
DARMExpandPseudoInsts.cpp1315 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1326 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1406 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1500 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
1684 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
DARMBaseInstrInfo.cpp881 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp()
990 } else if (DestReg == ARM::VPR) { in copyPhysReg()
996 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
DARMInstrMVE.td4478 // example when moving between rGPR and VPR.P0 as part of predicate vector
6597 let Defs = [VPR];
6709 let Defs = [VPR];
6756 let Uses = [VPR];
DARMInstrFormats.td226 // always either zero_reg or VPR, but needs to be modelled as an
/openbsd/src/gnu/llvm/llvm/lib/Transforms/Vectorize/
DVPlanTransforms.cpp115 for (VPRegionBlock *VPR : VPBlockUtils::blocksOnly<VPRegionBlock>(Iter)) { in sinkScalarOperands()
116 VPBasicBlock *EntryVPBB = VPR->getEntryBasicBlock(); in sinkScalarOperands()
117 if (!VPR->isReplicator() || EntryVPBB->getSuccessors().size() != 2) in sinkScalarOperands()
120 if (!VPBB || VPBB->getSingleSuccessor() != VPR->getExitingBasicBlock()) in sinkScalarOperands()
/openbsd/src/gnu/llvm/compiler-rt/include/profile/
DInstrProfData.inc457 getValueProfRecordNext(ValueProfRecord *VPR);
459 getValueProfRecordValueData(ValueProfRecord *VPR);
/openbsd/src/gnu/llvm/llvm/include/llvm/ProfileData/
DInstrProfData.inc457 getValueProfRecordNext(ValueProfRecord *VPR);
459 getValueProfRecordValueData(ValueProfRecord *VPR);
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp6247 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6268 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6461 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6946 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6983 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6994 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6995 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp3730 if (Regs.back().second == ARM::VPR) in CreateRegList()
3736 if (Regs.back().second == ARM::VPR) in CreateRegList()
4584 if (Reg == ARM::VPR && in parseRegisterList()