| /openbsd/src/gnu/llvm/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX904.rst | 36 VOP3P section in Instructions
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| D | AMDGPUAsmGFX900.rst | 36 VOP3P section in Instructions
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| D | AMDGPUAsmGFX1011.rst | 66 VOP3P section in Instructions
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| D | AMDGPUAsmGFX906.rst | 59 VOP3P section in Instructions
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| D | AMDGPUAsmGFX908.rst | 92 VOP3P section in Instructions
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| D | AMDGPUAsmGFX11.rst | 2611 VOP3P section in Instructions
2655 VOP3P DPP16
2666 VOP3P DPP8
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| D | AMDGPUAsmGFX90a.rst | 1583 VOP3P section in Instructions
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| D | AMDGPUAsmGFX9.rst | 1660 VOP3P section in Instructions
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| D | AMDGPUAsmGFX940.rst | 1582 VOP3P section in Instructions
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| D | AMDGPUAsmGFX1030.rst | 1833 VOP3P section in Instructions
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| D | AMDGPUAsmGFX10.rst | 1927 VOP3P section in Instructions
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 32 field bit VOP3P = 0;
114 // This bit indicates that this is a packed VOP3P instruction
170 let TSFlags{12} = VOP3P;
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| D | VOP3PInstructions.td | 10 // VOP3P Classes
66 let VOP3P = 1;
72 // Non-packed instructions that use the VOP3P encoding.
73 // VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed.
82 let VOP3P = 1;
958 let VOP3P = 1;
1192 let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 in {
1197 } // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1
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| D | VINTERPInstructions.td | 24 let Inst{31-26} = 0x33; // VOP3P encoding
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| D | SIDefines.h | 46 VOP3P = 1 << 12, enumerator
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| D | SIInstrInfo.h | 646 return MI.getDesc().TSFlags & SIInstrFlags::VOP3P; in isVOP3P()
650 return get(Opcode).TSFlags & SIInstrFlags::VOP3P; in isVOP3P()
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| D | VOPInstructions.td | 155 let VOP3P = 1;
914 let VOP3P = 1;
989 let VOP3P = 1;
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| D | AMDGPU.td | 385 "Has VOP3P packed instructions"
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| D | SIInstructions.td | 1715 // VOP3P instructions, so it is turned into the bit op.
2760 // FIXME: Should have VOP3P subtarget predicate
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| D | SIInstrInfo.td | 2143 // Returns the assembly string for the inputs and outputs of a VOP3P
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| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | AMDGPUModifierSyntax.rst | 1757 VOP3P Modifiers
1760 This section describes modifiers of *regular* VOP3P instructions.
1914 VOP3P MAD_MIX/FMA_MIX Modifiers
1919 in a manner different from *regular* VOP3P instructions.
2003 VOP3P MFMA Modifiers
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| D | AMDGPUOperandSyntax.rst | 123 Only VOP3, VOP3P and VINTERP instructions may access all 512 registers (using :ref:`op_sel<amdgpu_s…
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 330 if ((Desc.TSFlags & SIInstrFlags::VOP3P) || in encodeInstruction()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 462 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) in getInstruction()
828 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { in convertDPP8Inst()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 3475 SIInstrFlags::VOP3 | SIInstrFlags::VOP3P | SIInstrFlags::SDWA)) && in validateConstantBusLimitations()
4068 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()
4239 (TSFlags & SIInstrFlags::VOP3) && !(TSFlags & SIInstrFlags::VOP3P)) { in validateOpSel()
4284 if (!(Desc.TSFlags & (SIInstrFlags::VOP3 | SIInstrFlags::VOP3P)) && in validateVOPLiteral()
8769 if (Desc.TSFlags & SIInstrFlags::VOP3P) in cvtVOP3DPP()
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