| /openbsd/src/gnu/llvm/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 36 TIED_TO = 0, // Must be allocated the same register as specified value. enumerator 42 ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 1069 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias() 1074 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) in getOperandBias() 1079 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias() 1080 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) in getOperandBias() 1084 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias() 1085 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || in getOperandBias() 1086 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) in getOperandBias()
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| D | X86InstComments.cpp | 271 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1) in printMasking()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| D | SystemZHazardRecognizer.cpp | 127 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in has4RegOps()
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| D | SystemZShortenInst.cpp | 69 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 && in tieOpsIfNeeded()
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| /openbsd/src/gnu/llvm/llvm/tools/llvm-exegesis/lib/ |
| D | MCInstrDescView.cpp | 121 int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO); in create()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 217 if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1) in ClusterNeighboringLoads() 455 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
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| D | ScheduleDAGFast.cpp | 252 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
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| D | ScheduleDAGRRList.cpp | 1039 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in TryUnfoldSU() 2850 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { in canClobber() 3090 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) in AddPseudoTwoAddrDeps()
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| D | InstrEmitter.cpp | 359 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 204 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl() 209 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
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| D | MachineInstr.cpp | 265 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() 1506 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); in hasComplexRegisterTies()
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| D | MachineVerifier.cpp | 2022 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand() 2079 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) in visitMachineOperand()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 530 assert(OpDesc.getOperandConstraint(Component::SRC0, MCOI::TIED_TO) == -1); in ComponentProps() 531 assert(OpDesc.getOperandConstraint(Component::SRC1, MCOI::TIED_TO) == -1); in ComponentProps() 532 auto TiedIdx = OpDesc.getOperandConstraint(Component::SRC2, MCOI::TIED_TO); in ComponentProps()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 691 MCOI::OperandConstraint::TIED_TO); in getInstruction() 804 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { in isMacDPP() 808 MCOI::OperandConstraint::TIED_TO) == DST_IDX); in isMacDPP()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 190 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 6418 Desc.getOperandConstraint(Inst.getNumOperands(), MCOI::TIED_TO); in cvtDSImpl() 8085 MCOI::OperandConstraint::TIED_TO) == -1; in isRegOrImmWithInputMods() 8716 Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1; in cvtVOP3DPP() 8739 MCOI::TIED_TO); in cvtVOP3DPP() 8805 MCOI::TIED_TO); in cvtDPP()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 2651 MCOI::TIED_TO) != -1)) { in findCommutedOpIndices() 6112 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; in foldMemoryOperandImpl() 6227 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO); in foldMemoryOperandImpl() 6229 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO); in foldMemoryOperandImpl()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1178 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in commuteInstructionImpl()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1017 int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO); in AddThumbPredicate()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 5255 (MCID.getOperandConstraint(i, MCOI::TIED_TO) == -1) && in validateInstruction()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 2508 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); in addVPTPredROperands()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 12276 int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO); in AdjustInstrPostInstrSelection()
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